FIFO as a Logic Analyzer; Clock synthesizer

Apr 21, 2005 2 Replies
T

I would suggest that you not even use a header cable. Put the FIFO in the probe.

If you really have to use buffers and cables, LVDS is the way to go.

How variable? I'm guessing that you want to cover several decades (=

10 octaves). If just powers-of-two are OK, there are oscillator cans in the 166 MHz region and you can select off a tap from some ripple divide-by-twos.

I've been having a lot of fun playing with the AD9954 series DDS's. The 9952/9954 have comparators just for clock generation. 166 MHz is just over the top of the official spec although I'm sure it'll work. Circa $25 for the chip from Digikey, then a crystal and some L's/C's.

Tim.

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M

Putting the fifo as close to the signal is an excellent idea. The default way to make a multi-twisted-pair cable guarantees horrible inter-channel skew.

But you should also provide input buffers or protection of some kind. Sooner or later, a probe will brush across something outside the 0-5V range and make smoke of your neato-keen FIFO. mike

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N

Hi! I have a big FIFO chip covered by dust, that I'd like to finally use. The most useful application I'm imagining for it is to finally make myself a logic analyzer. This FIFO (Texas Instruments SN74V3690-6PEU) is a 3.3V device, but has 5V tolerant inputs. "Great!" I thought.



What I'm asking you is: should I connect the probes (just a header cable) directly to the FIFO, or should I use an high speed buffer inbetween? Consider that the chip is specced at 166MHz.



Moreover, what is the cheapest way to produce a variable clock speed up to 166MHz (and possibly beyond, for other applications)? A PLL? Any chip you may suggest me?



Thank you! TPM



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