Intel's business model doesn't work in the mobile market, or any other than the classical desktop/laptop market. They want to suck all the profit out of the platform. Why would the mobile device makers put up with that when there is a perfectly acceptable (and perhaps superior) alternative?
If' I remember correctly from my previous life as an HVDC control systems engineer, deionized water can actually be quite corrosive, so it's not necessarily the first option I would consider.
Water, even de-ionised, is an ionising solvent, and at room temperature contain about one part in 10^-7 of OH- and H30+ negative and positive ions.
Any metal more electropositive than hydrogen can steal oxygen from a water molecule, form an oxide and free hydrogen.
In that sense, it's corrosive. Quite a few metals are self-passivating, in that the initial oxide layer is stable and coherent, and stops the water getting at the metal underneath, so you've got a reasonable choice of materials it won't corrode.
-- Bill Sloman, Sydney
I guess that is not a bad way to put it. Two decades ago TI changed their business model to make DSP chips for the cell market and they steered the entire company in that direction selling off memory and other parts while buying support chip products like ADC-DAC and power conversion device companies. It worked great for awhile, but ultimately the market matured to the point that DSPs are now rolled into the greater chip set of the smart phone where the phone section is not the major part of the device.
In a similar manner the mobile CPU market has matured to where phone and tablet makers don't necessarily *buy* CPUs rather than simply make their own custom devices. This means they use ARMs rather than anything Intel because Intel's idea of the market is to tell the customers what they can have rather than asking what they want.
-- Rick
John,
I know we can't feed FPGA clock with sine wave.
My question : Why do you plan to divide and the drive the initial 600MHz near the oscillator ?
My idea is that it's better to route the prime sine 600MHz through the PCB layers (optimally) and divide it near the FPGAs for clocking. I think the advantage is that a pure sine wave is much easy to adapt on PCB context than square waves (delays, reflexion, ... matching impedance ... matching loads ...etc.) pppfff i'm tired !
Habib
A balanced sine wave as a differential pair of complementary signals on a p air of close-tracked buried strip-lines isn't going to interfere with anyth ing, and a differential ECL line receiver will reject most of what it might pick while squaring it up in the process, but there's no obvious reason wh y John's 600MHz since oscillator can't be fairly close to his FPGA's anyway .
-- Bill Sloman, Sydney
Bill,
Ok. Regarding JL's issue, what sort of architecture of clock distribution will you adopt ? I suspect John has to be sure the FPGAs are clocking synchronously ... although it is obvious that internal re-synchronous statements (verilog/VHDL) are mandatory ... may be.
H
If an FPGA has an LVDS clock input, a sine wave there should be fine. But since I plan to divide the 600 MHz by 4 or 8 before using it as a clock, the FPGA will bet differential PECL.
As opposed to far away? Gotta put the divider somewhere, may as well be close to the oscillator.
Sine waves have all the reflection and termination problems of square waves.
If I use the 10EL34, I can get /2, /4, and /8 clocks from one chip, really close to the oscillator.
With fast stuff like this, you have to design the schematic with the layout in mind.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
Is that a rudimentary ALU? Is it available in surface mount?
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Sure, if the surface is a raised computer room floor capable of supporting
5 tons in about 15 square feet!Jon
Am 18.01.2016 um 17:34 schrieb John Larkin:
With square waves you have to be more careful since the phase of the harmonics modifies the trigger level / time when they change. So, a greater bandwidth is required. There is an interesting paper from the time/frequency group at NIST that deals with I/O termination of precision isolation amplifiers in the light of this.
But it should be possible to handle that on a board.
regards, Gerhard
I'm not completely sure if I meant this one; there is more:
The Effect of Harmonic Distortion on Phase errors in Frequency Distribution and Synthesis
F.L. Walls* and F. G. Ascarrum'
Here is one of our pick-and-place machines:
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
True, square waves can have ringing that sine waves don't.
I don't expect problems routing differential clocks in the 100 MHz ballpark. Or even single-ended, but diff generally has better jitter and time/tempco behavior.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
TI makes SOCs with multiple ARM cores and several DSPs, originally for the mobile phone market but also for others.
Sure, with a market that size, why give anyone a piece of the action. The CPU and DSP cores are readily available. It's not a big stretch for anyone with pockets as deep as the (few) mobile phone markets to stitch them together into an SOC.
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4Hz
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a pair of close-tracked buried strip-lines isn't going to interfere with a nything, and a differential ECL line receiver will reject most of what it m ight pick while squaring it up in the process, but there's no obvious reaso n why John's 600MHz since oscillator can't be fairly close to his FPGA's an yway.
Not a question I can usefully answer, since I haven't got a clue about the details of what John Larkin is trying to do, or why he thinks he needs to d o it that way.
ON-Semiconductor does offer a range of clock distribution chips, which take one input and generate a number of fairly closely synchronous outputs - wi th fairly tight specifications on propagation delay and on propagation dela y spread between outputs.
As a general rule, you don't want more than one load on any single clock li ne - though I've done it (and shaved the appropriate length of the transmis sion line fro 50R to 75R to compensate for the capacitive load presented by a single ECPinPS gate - a cm or so).
-- Bill Sloman, Sydney
Differential clocks have twice the amplitude, so jitter has to be a least h alved when compared with a single-ended clock - more if your balanced to si nge-ended receiver has any common mode rejection.
It's less obvious that differential clocks will have more stable propagatio n delays against temperature. If the local threshold for a single-ended clo ck isn't properly centred on the actual clock swing, that could introduce a temperature dependent extra propagation delay error, but that's about it.
-- Bill Sloman, Sydney
The issue is not frequency, but rather edge rate. Will your 100 MHz clock have a slower edge rate than a faster one? If not it won't be any easier to route than a fast square wave. The problem with square waves is you can get double clocking when the edge is no longer monotonic from the distortion/reflections.
-- Rick
Yes; i heard that those were WSI (Wafer Silicon Integration).
Definitely would need to run the water thru a de-ionizer and keep "pipes" as short as possible; may need multiple paths for a "large" system.
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