Interestingly that isn't so. I knew a bunch of the people writing the run s heets for the last couple of generations of IBM's ECL machines. They were b ased on the ATX4 and ATX6 processes, and a finished ATX run sheet had over
600 process steps vs less than 300 for contemporary CMOS logic.Fujutsu/Amdahl stuck with bipolar for one more generation of machines after IBM went to air-cooled CMOS, and they ate our lunch for a year or so as a result.
Cheers
Phil Hobbs
I'm still in the brainstorming stage, but the idea is to have a 600 MHz sinewave oscillator that needs to be divided down and distributed about a board. An ADCMP-series comparator can make the sine wave into PECL, then a PECL Johnson counter can do the divide. The divided PECL can go straight into FPGA differential (LVDS) clock inputs and other places. Most LVDS receivers will happily accept PECL.
The PECL Johnson counter would have tiny prop delay and low delay vs temperature. And lots of fanout possibilities. I'm doing picosecond timing, and CMOS has terrible delay vs temperature behavior.
I was wondering if anyone here was designing with ECL. Sounds like not.
I wish someone would make an LVDS logic family, a few gates and flipflops. There are buffers and a few clock divider/fanout chips.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
Looks like them sumbitches were wired point to point between the stacked cards, as well, with every wire cut to just the right length to mimimize transmission line effects.
Wow. It's amazing that my iPod Touch likely has more compute horsepower. Wonder if I could run nuclear weapons simulations on it.
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More precisely to *use* transmission line effects (delay).
Not without the NSA knowing. ;-)
Interestingly, "complexity" has more than one meaning. Complexity of the processor/logic is what I meant. There's no way you could stack enough ECL gates together (and power them up), even if you could manufacture them.
Yes, IBM switched to CMOS one generation early. It was clear that bipolar was out of gas but they couldn't get the same performance (yet) out of CMOS. Another generation of ECL machines didn't justify the expense required so the decision was made to switch to CMOS and pretend they were just as fast (maybe the customer won't notice). I was in the middle of the whole thing (just before the MHV imploded and I moved to BTV).
Am 16.01.2016 um 19:04 schrieb John Larkin:
I do now and then. Precision timing.
No, please not. The zoo is big enough. We have 10K/100K/compatible, NECL / PECL with 2.5 / 3.3 / 4.5 / 5.2V / CML in several voltage flavors. That's too much already.
I have just opened my Agilent 54846B scope to change the CMOS RAM battery. The is _a_lot_ of ECL inside.
regards, Gerhard
John,
If I understand you want to generate a sine wave from a ADCMP comparator output. Right ? Then you should have to feed the Low Pass filter input with the square output comparator ...
Please John tell me what sort of low-pass filter you have in mind ... just for my knowledge. No offense please.
Habib.
Is it a FR4 PCBoard ?
No, I will have a sine wave oscillator, and I want to square it up into a logic signal, divide it some, and distribute it around a board. Maybe I can use an MC10EL34 to do the divide.
Still, ECL.
Yes, optimistically 6 layers, maybe 8 if things get tight. FR4 seems to work fine with fast logic signals.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
As long as military situations regularly occur in the world and we can't mothball all missiles and stuff it very likely will remain available. Pricing is a different ballgame though.
-- Regards, Joerg http://www.analogconsultants.com/
Sure!
CERN has a few @Home type projects listed!
Although none of them show ARM platform support, so you'd technically have to emulate x86... ew. Or write the core yourself, perhaps.
As for computers, it is rather impressive that a 2W, $10 microcontroller today has more power than a 100W, $500 microprocessor 2 decades ago, or a
10,000W, $500,000 supercomputer from 4 decades ago.And the information-theoretic compute limit is still something like 6 orders of magnitude left to go.
Tim
-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: http://seventransistorlabs.com
When I last looked - in about 1998 - you could buy crystal oscillators - using etch-thinned silica crystals - to run at up to 600MHz.
I was actually planning on buying a packaged oscillator with balanced ECL outputs.
Epson does SAW oscillators from 100MHz to 700MHz. From memory SAW oscillators were only available in small quantities at a few frequencies - if you wanted something specific you had to pay for a batch.
PECL is a bad idea. If you short an output ground, it blows up. Running ECL between 0V and -3.3V is much safer.
You do have to put in level shifters to move the signal up to regular logic levels, but they are cheap and freely available, and the one's I used were insensitive to noise on the +5V (it was that long ago) and produced clean fast edges.
is fast enough, but ON-Semi do offer faster parts
-- Bill Sloman, Sydney
I want at least three of them to speed up Spice.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
EXACTLY! Actual current should be well under one amp.
The Cray 1 was SSI ECL, but a very fast version custom made for Cray. It was liquid-cooled, but not in a direct bath. Some kind of Freon material ran through vertical cold plates on both edges of the vertical stacks of circuit boards. The board assemblies were essentially two boards clamped to a central cold plate that interfaced to the big vertical cold plates. These cold plates were also used as an additional logic ground.
Later Cray machines immersed the entire CPU in boiling fluorinert coolant, as they had much higher power density than the Cray I. I think these were also a flavor of ECL, but a higher level of integration.
Jon
Sure, if running in the Motorola-suggested scheme for ECL 10K of ground and
-5.2 V, then the logic levels are -0.8 and -1.6 V. Termination of the outputs can be to -2.0 V, or with some degradation of logic levels, to
-5.2 V. ECL 100K is a little different. IBM in their MST, and some other users run ECL at voltages like +1.25 and -3.0, which puts the termination at ground level. Then, the logic levels are about -0.4 V and + 0.4V.
If speed isn't that critical, the 10124 and 10125 chips interface ECL to nominal TTL levels.
Jon
That's too bad. Didn't Intel try to get into the mobile market...Intel Atom or something?
x86 seems DOA as a mobile processor architecture, seriously.
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The 10124 and the 10125 - and their more modern equivalents - are quite fast.
It's the TTL that used to be slow, but some flavours of CMOS are quite quick, if unsuitable for driving terminated transmission line links.
-- Bill Sloman, Sydney
How about immersing PCBs into (deionized) water ? At least it seems to work in HVDC switches with hundreds of kV between bays.
I recently saw a film from Russia with some equipment with regular looking gear immersed into an open tank with some clear liquid, claimed to be water. At least some LEDs were blinking, so some activity on the PCB :-).
I don't understand how long that water would have remained deionized in an open tank, but perhaps the lid was taken off for the filming.
What would be required to run a system in deionized water ? At least non-hydroscopic PCBs ? Coated PCBs ?
What else ?
What do you actually need, a 50:50 duty cycle phase shifted outputs or individually decoded 25:75 (or 12.5:100) decoded outputs ?
A divide by 4 would simply be 2 bit flip-flop and a single package with four 2 input gates for decoding individual states. With all decoding done in a single chip, I do not see how serious temperature related problems would occur.
For the divide by 8, four flip-flops would be required, possibly as a
4 bit shift register with balanced outputs from each stage and two quad packages with 2 input gates for decoding. Having two decoder chips would potentially give some delay problem, but placing the decoder chips symmetrically to the counter chip would help somewhat.A quick search brings up several flip-flops and gates operating at several GHz, so your 0.5 GHz requirement shouldn't be too hard.
Oh i see ! Is it more quiet in EMC point of view to distribute sine wave through PCB layers and after "square and divide" near the consumer ?
This for kill all impedance terminations and other stuff like that ...
Please take a look at Pericom products, they have some nice clock buffers (diff pair outputs) designed with the LVPECL techno, don't if they fulfill you design requirements (< ps skew ...).
Distribute a GHz signal from one output to many inputs through PCB layers is very tricky .... we did it years ago at Kontron (PPC DDRII memory banks) simulated with SI Hyperlinks ; when testing PCB implementation we all became depressed at the eye diagram of signals DQS, /DQS, CK, /CK ...etc. Although all were working like a charm.
H.
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