ECL

It's easy enough to a differential pair level shifter with pair of 5GHz wide-band transistors - BFR92 (NPN) or BFT93 (PNP). I've done it where I didn't want to make space for a quad level-shifter package.

With fast transistors it's easy to match 100k ECL speeds. I haven't done it with ECLinPS, but it ought to be good enough. John Larkin does that kind of stuff, and has done for years.

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Bill Sloman Sydney

Bill,

Sure it is. I did not remember i have been arguing otherwise, the trick is how to maintain jitter with discrete components for a diff pair. A strict geometry beetween BJTs is mandatory to reach good phase noise

BR, Habib

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use oil instead:

-Lasse

How does 115kW work for you, numbskull?

All the big kids (like Cray mentioned above) use one or another Fluorinert:

The klystrons used in communications links through the 1990s lived in a tank of Fluorinert with a pressure regulating bellows to maintain a constant boiling temperature.

Same stuff is used in vapor-phase solder reflow systems:

It's the "right stuff", you know.

--
Grizzly H.

First off, Cray did NOT "immerse the entire CPU in boiling fluorinert". They immersed their CPUs in fluorinert and THEN they proceeded to cause it to boil, ya bunch of dummies.

Water? No way, because what may start out as "deionized water" will almost immediately become ionized in contact with all of those metals. DOH! Bad move. Probably why NOBODY does it.

Oil? Fuck oil, the fluorinert is fine and it can be chilled. It is far closer to a refrigerant than oil is and can carry the heat off better too.

And the term is hygroscopic and all PCB strata that I know of is short of flex assemblies.

Am 17.01.2016 um 14:37 schrieb Lasse Langwadt Christensen:

No. FR4 soaks up mineral oil and swells, to the point of cracking the vias. Fumes are enough.

We had to use Kapton boards for our pipeline pigs. Kapton prepregs have a very short shelf life. Watch your supplier that you don't get old stuff.

regards, Gerhard

The prime signal source is a 600 MHz oscillator, which is nearly sinusoidal, but all the various loads are digital. I can't clock an FPGA at 600 MHz, so we need to divide by 4 or maybe 8 to clock logic. The divider and drivers will be very close to the oscillator. MC10EL34 is almost perfect as the divider, excepting one unnecessary clock delay at startup.

There are a few nice LVDS fanout chips around, some with dividers. ADI, TI, Cypress, ONsemi, IDT make some too. There are also single LVDS buffers, like FIN1101, a nice little part. LVDS is really slick, and is nearly compatible with PECL.

LVDS is a little mysterious inside. The gory details of driver and receiver internals are obscure, unlike ECL, where the data sheets often show the transistor-level guts. We have to measure LVDS parts to understand their behavior.

Well, it's hard to probe things like diff PECL and LVDS and PciExpress, so the signals may well be better than they look. A reasonably routed differential pair on FR4 can do a very nice job of sending a 600 MHz clock several inches across a board. Multi-GHz data is a different story, but equalizer chips can fix that too.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics

That's weird. ECL can only pull up.

We almost always use ECL in PECL mode, with a positive Vcc supply and pulldowns to ground. Vcc is usually 3.3 or 2.5, and Vee can be ground for newer (10EP) parts. Most FPGAs will accept differential PECL as inputs, and PECL and LVDS are pretty friendly.

The original 10H124 is terrible, slow and lots of jitter. An LVDS receiver is a better and cheaper way to get to CMOS level.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics

SN65LVDS2 does pretty fast diff-to-cmos, SOT23, about 60 cents.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics

You'd need a good deionizer system, and maybe to add something to the water to scrub whatever might cause problems. Boards could be conformal coated, but that would interfere with heat removal. Connectors would be the hardest part to keep free of corrosion, etc.

The military and aerospace people have been making conduction cooled electronics for years.

Jon

Right, that's why they have to run the collectors of the chips at +1.25 or

+1.3 V. Then, they need a heavy pull down resistor to -3 V, I guess, so that the low logic level will still be drawing sufficient current through the emitter follower output. They used 98 Ohm terminators on MST systems, so that would get about 4 mA for either logic level (opposite sign). So, for the low logic level, the terminator would be sourcing 4 mA, so you'd probably need to pull down with about 8 mA at 3 - 0.4 = 2.6 V, for about 325 Ohms. For the high logic level, the pulldown would be sinking 10 mA, the terminator sinking 4 mA, so the emitter follower would be carrying 14 mA. Well, that's why the IBM 370's ran hot!

Jon

I'd have to dig into a data sheet or even contact an FAE to see what variations will be seen, but you can get much more precise output timing using the internal PLL and FFs in the IOBs. You don't have to use internal FFs which are then run down a long route and through the IOB buffer.

500 MHz is possible but pushing most FPGAs. It would be an interesting project to work on.

--

Rick

This stuff was over the top. I worked for Star Technologies that built a 100 MFLOPS machine cooled by air which cost $250,000 with minimum memory. They used ECL gate arrays rather than SSI level ICs and later produced a 50 MFLOPS version using CMOS gate arrays which fit in a single card rack with 9U Eurocards. Considering the difference in price and size these were much more effective units.

--

Rick

Right, Seymour Cray was using old, familiar technology that I assume he knew was heading toward obsolescense. But, he had a window of time to get a REALLY fast supercomputer out the door, and he wanted to do it. He knew he could make this technology work, without having to INVENT a new technology, which he didn't have the money or the time for.

Remember the first Cray-I was installed in 1976!

Jon

According to Motorola, PECL cuts into the noise immunity fairly badly. For some special app where one ECL chip is needed, you can manage with it. But for a system with MANY ECL chips, it makes more sens to use one of the other schemes. Those also make the termination easier to deal with.

Jon

ON-Semi has a whole menagerie of ECLinPS dividers. What's special about the MC10EL34 - and don't they do an MC100EL34 with better temperature stability?

offers it.

One time I did an ECL version of a previously TTL board, the original designer got me to buffer the crucial signals with BFT93 emitter followers so he could probe the circuit without messing up the signals ...

So can better board materials. FR4 is dispersive a GHz frequencies. Rogers

sells substrates that are much less dispersive. Microstrip transmission lines are intrinsically dsipersive, so you ought to use buried stripline (which isn't).

--
Bill Sloman, Sydney

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It's not weird, but rather clearly wrong. The terminations would have to ha ve been pulled down to -0.75V (or lower) if the ECL were run from +1.25V an d -3.0V.

The problem with PECL voltage levels - +5V and 0V or +3.3V and 0V is that i f you ground PECL output you'll most likely blow it up - the old Hewlett-Pa ckard laser interferomenter did that and almost all their service returns w ere caused by that (even though they used very little ECL).

Maybe +1.25V isn't high enough to blow up the output transistors if you sho rt the emitter to ground.

The original MC10H124 is terribly old - around 1980 or earlier. There have been a couple of generations of improvement since then.

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Bill Sloman, Sydney

If you are running ECL off a TTL power rail, you have to cope with the fact that TTL power rails are horribly noisy, which is reflected directly in your PECL output levels (which are tied to the positive rail).

PECL may be a cheap way to incorporate ECL in a basically CMOS/TTL system. but it's also nasty.

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Bill Sloman, Sydney