ECL: Why'd they use negative voltages?

Noise immunity is better with 0/-5.2V

I was there when they (Narud, Seelbach, Philips, et al) did that. ...Jim Thompson

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| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
      The only thing bipartisan in this country is hypocrisy

As Jim said, noise immunity. But also from itself. The upper transistors are the most prone to generate transients in ECL, so it helps if their collectors tie right into chassis. In the old days 4-6 layer boards were unheard of. All you had was 2-layer phenolic, and only if you were lucky. Nowadays that's not an issue anymore because the +5V plane in a PECL scenario is just about as good an RF sink as the ground plane.

Why 5.2V I don't know but 6.3V is not an arbitrary voltage, just like

12.6V isn't. That fit the typical car battery voltages just right. So you could hang the filaments straight onto the battery voltage and only had to generate the plate voltages. That was initially done with a mechanical switcher where the "buzzer cartridge" would wear out once in a while.

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Regards, Joerg

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0V for ?

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More specifically, the output's Vcc rejection =3D 0 (the driver's collector resistors ferry Vcc noise straight-thru). Or did you mean something else, another gotcha?

Hypocrisy may be bipartisan, but the two camps--socialists vs: free market--are critically different, and not even totally defined by party.

GWB spent like crazy. Ahhh, those were the good old days, of fiscal prudence...

-- Cheers, James Arthur

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

Was the whole idea (just keep the transistors operating in their linear regions rather than saturated or cut-off -- sacrificing power consumprtion for speed) pretty much self-evident to everyone at the time, and it was just a question of convincing enough people of the viability/marketability of the technology so as to get the money for funding all the development -- or was it instead a pretty novel idea, that few people had really thought about and developed up until that point?

Thanks,

---Joel

Original ECL had no current mirrors, just resistors, thus -5.5V gave the nicest (but still crappy) TC.

Later on there was 10K/100K. My biggest challenge was making a threshold specification bracket overlay that would display automatically in PSpice simulations :-) ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
      The only thing bipartisan in this country is hypocrisy

Add to the above, shorting the common emitter outputs to ground isn't damaging.

Stack up the voltages (don't forget the AND gate).

Not all ECL was the same, though. Our high performance ECL ran off +1.25V and

-3V, with the outputs around ground.

Of course not. 12.6V is twice 6.3V. ;-)

Ah, gotcha -- that makes a lot of sense. "Ground is ground, but 5V (or 5.2V or whatever) tends to 'wiggle around' rather more..." (Especially in that the earlier ECL series where VBB wasn't actively regulated against supply voltage variations.)

Hmm... 13.8V = car running w/alternator floating a 6-cell battery and 12.6V = car turned off, battery powering radio then?

Thanks,

---Joel

Yep. Current mode is fast... better power-speed curves than CMOS at really high speeds.

It was military funded: Wright-Patterson funded all my flash ECL A-to-D's. ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
      The only thing bipartisan in this country is hypocrisy

I forgot to mention: Some ECL line drivers featured a positive voltage for the collectors of the output followers. It was NOT low power, but it sure as hell was fast :-) ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
      The only thing bipartisan in this country is hypocrisy

Purportedly it'll run down to around VCC-VEE = 3V and up to about 8V before you start seeing massive performance differences. 5.2V is certainly pretty close to the center of those two... hmm... I wouldn't be surprised if that's how they came upon it!

The output swing and receiver threshold are relative to the chip Vcc, the nominal logic threshold being about 1.35 volts below Vcc. That's basic to the circuit topology. At these speeds, and with 0.8 volts of swing, it makes sense to refer the swing and matched-impedance traces to a quiet solid ground plane, so Vcc=0 volts makes sense. ECL chips aren't very sensitive to Vee.

10KH type ECL does work fine at Vcc=5, Vee=0. That's called "PECL" mode, originally "pseudo ECL" and lately "positive ECL". One generally references all the signals to a nice 5-volt copper pour.

Don't know why 5.2, and not just 5.0.

Newer stuff, like EclipsLite, works at 3.3 volts, and some at 2.5. I do mixed-mode PECL and cmos/FPGAs off a +3.3 volt supply.

John

Those often didn't afford us the luxury of a VBB output even being there.

The first cars were all 3-cell and then there's wiring losses and all that. Back then dropping a voltage was easy, raising one was next to impossible. And cars had DC generators. In fact, my old Citroen did as well. Crankshaft-driven, no belts in the whole car.

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Regards, Joerg

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I think what might have once been largely a bimodal distribution is now converging towards a normal distribution, James... albeit with two additional little spikes close to either end as well. :-)

I fully expect that given some centuries or perhaps even a few millennia we're going to have a single world government anyway, most people will be some shade of tan without very distinctive physical attributes, etc.

Although apparently a lot of people back in the FDR's day felt that this would have already happened by 2000...

---Joel

+2 and -3 allow terminations to ground. Terms are where most of the power goes.

John

No, Jim had the reason above. Try an AND gate at 3V. ;-)

Thanks John, that's quite informative.

That's kinda what prompted the question -- Joerg has been pointing me at some of the high-speed logic from the likes of Micrel, and I was reading up some in the old MECL System Design Handbook so that I hopefully won't embarrass myself too badly when I go to use some of it. :-)

---Joel

Seems like a belt is an awfully inexpensive addition for the flexibility it provide in terms of being able to locate and size your generator independently of the engine itself, to a large extent!

MC10EP05.

John