Dumb question regarding SMPS

The challenge is always with switchers. The upper FETs of a bridge or sync-buck are easy, I just use a V+ plane. The lower ones hang on the switched node with their heat-carrying drain tabs. That is a real pain because normally you don't want to make that very capacitive.

Modern datasheets are notoriously incomplete. Even uC with their hundreds of pages. They discuss the logic stuff ad nauseam and then, if you are lucky, you find one or too sparsely populated pages on the ADC.

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we have everything modeled in inventor, pcb with components, enclosure, connectors etc.

so we know it will fit in the box, there's room for the connectors etc.

-Lasse

No, just the schematic library part and footprint. A hundred pins, most of which have names like this:

(OC0A/OC1C/PCINT7)PB7

One typo and all hell can break loose because the routing resources in those uCs are sparse and can be unforgiving. Just had a major re-shuffling in one of them on another project, not because of an error but for a feature change. When those get maxed out in port pins the design can slow down as much as Van Ness at rush hour, mainly because of routing compromises.

Yikes!

Don't know about this one but sometimes with eval boards I have the feeling that they aren't always super great. I remember one where I fired it up, ran it with standard load and then caught a whiff of an "amperage smell". Followed by smoke. That was the snubber resistors turning themselves into charcoal. Another board ... one minute, two minutes, three ... *PHHHHUT* ... a diode had left its workplace without prior authorization to do so. A quick calc revealed a 3x or so overload. Luckily I found its pieces on the floor before a guide dog puppy we had for a week.

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Like, how much power does the ADC reference need? Not a clue.

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looks like they just more or less copied the layout from the packages that don't have a thermal pad

strange how eval board are often like that, would think they wanted to present their part in the best possible way

can only guess they assume those who need the performance will build their own board anyway and those who buy the eval board generally won't notice

-Lasse

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Wot reference? Sometimes they think that VCC _is_ a good-enough reference. Sometimes we've had to do ratiometric conversion just because there wasn't even a pin to pipe in your own reference.

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Considering the quality of most uC ADCs, they're not far wrong. ;)

Cheers

Phil Hobbs

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Actually some are not bad at all. Otherwise they would not pass muster with agencies when they are placed in metering applications. Often it is important to halt processor activity during a measurement, that can make a huge difference. This is what we'll likely do for the project I am working on right now.

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You *should* be able to either grab the names from a spreadsheet or cut-n-paste from a datasheet. The vendors often have models already built that can be used for a starting place, too. OTOH, our CAD people demand that chips look on the schematic like they do on the board - no functional partitioning (except BGAs, for some reason).

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Or a hundred pages on register settings and one or two pages on the hardware itself; worse, the hundred pages isn't even complete.

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Only for some CAD packages, if at all. My CAD has a lot of the Atmels, just not this big one.

I insist on the same, I really hate netlist-style schematics where the front axle is on page 17 which the left front wheel it on page 32. Exceptions are logic gate and opamp multi-packs, of course. And I never use large BGAs, those can spell doom in a hi-rel environment.

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Yup :-(

Very classic omission: Do the ports have input hysteresis or not? And if yes, how much? Once the answer from the tech support engineer, after long head-scratching, was: "Good question! I'll have to inquire about that at the factory". Oh man ...

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H, our CAD people demand that

isn't reliabily and BGAs something that was perfected many years ago?

for something like a big FPGA I think it it makes sense to put core power, jtag configuration and such on one symbol and each bank on a separate symbol

-Lasse

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It's the ATMega2560.

I do not trust them. Seen way too much grief with BGA. Most of all, I do not like something where solder connections cannot be inspected with reasonable effort. Large rigid structures with next to nothing in compliance on a flexible material (FR4) are IMHO a bad idea.

That may be ok. But I really do not like it when, for example, the various UARTs of a uC are sprinkled across several schematics pages.

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Buy me enough beer, and I'll tell you tales of polynomial curve fits... one for each uP on a board with 12 uPs.

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I get the feeling that complex uP chips contain big blocks of purchased IP, sort of shoveled into the cement mixer. ADCs, Ethernet, USB, PCIe, whatever. Maybe the factory can't help much.

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Not the CAD companies. The chip manufacturer often has CAD symbols and footprints for the popular CAD packages. They usually support the common packages. Others can often import the data from that data.

Of course not. All the wheels go on page-1 (with the tires/wheels/and nuts in the hierarchy on page 2-5) and the Engine goes on page 12, with the exhaust on page 88.

Gates and opamps are drawn symbolically but everything else is a single physical square box. UGH! It makes *really* ugly schematics. Impossible to follow.

Nonsense. I did a bunch of MIL stuff (Naval weapons system) with 1k pin BGAs. Fine pitch isn't so good but there's nothing wrong with >.8mm BGA packages. Doom comes before the design starts, without them. No project = no paycheck.

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Sure, at least in the larger packages. Joerg is living in the '80s. They even worked well then but many didn't have the process down.

Agree 100%. Even "small" 144-pin QFPs are a mess when they're shown as one big box on a page with wires everywhere. Joerg probably doesn't like busses, either (someone here objected to them a while back).

I often break FPGAs up by I/O bank, if I haven't got the design very far along. If know how it's going to flow, I'll break it up that way. I can still do that with BGAs, but not QFPs or QFNs. The CPoE has some really strange ideas on how a schematic is to look. The CAD system sucks, too, but that's a different topic. ;-)