Dumb newby has a question...

First approximation, low frequencies,

Vgain = Gm * Rl

where Gm is transconductance in mhos (or Siemens, if you prefer) and Rl is the drain load resistance (or impedance.)

A bit more precise would be to look at the slope of the drain curve, convert that to resistance, and put that in parallel with Rl to get effective drain resistance Rd, then

Vgain = Gm * Rd

which will be somewhat lower than the first equation. If Rl is small,

1 k or thereabouts, you can ignore the drain resistance thing.

At RF, the drain load gets harder to compute and the capacitances start to matter, so it's not as simple.

John

They didn't put that in because it depends on the load resistance and frequency (see John Larkin's answer). At high frequencies it also depends heavily on board layout.

So it's traditional to just include what you got, and leave it to you to design your circuit.

See if you can get a copy of the ARRL Handbook -- last time I looked they still had a pretty good basic theory section for transistors.

--

Tim Wescott
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Hey John,

Yeah, that is basically what I found in Practical RF Design Manual by Doug DeMaw, although it was a little more complex. So, basically there aren't any charts/graphs that give even approximations of common-source voltage gain at RF, like even 10 MHz? (Guess that's why I can't find it.) I was wondering if I was missing something in the transconductance/transadmittance thing. So have I found my answer, it's just not as easy as I wanted?

Thanks much,

Dave

Hey Tim,

Hmmm. The ARRL Handbook is the one place I don't think I have looked for this question. Have my copy in the other room, will go check it out. Thank you. Told you I was a dumb newby... (shaking head.)

Thanks much.

Dave

RF part datasheets will sometimes have S-parameters, which give you power gain versus frequency for 50 ohms in and out, and corresponding input and output complex impedances. That's enough to figure out actual RF gain in most situations, but it's not real simple. Bowick's paperback, RF Circuit Design, is a good place to start if you want to get serious about this.

10 MHz isn't super-fast, so Gm * Zl will sorta work.

If this stuff was easy, anybody could do it, and we wouldn't want that, would we?

John

It's not quite that easy. Yes, G = Gm * Z_load, but the trick is figuring out the value of the transconductance, Gm. Dave, we should mention that Gm depends on the JFET's operating current, Id. We can write Gm = 0.025 Id/n, where n is a gain-reducing parameter that we hope is nearly constant for a given part, it least at modest currents. I've seen n range from 4 to 200. Let's examine the 2n5486 datasheet.

For the 2n5486 we see Gm ranges from 4 to 8 mS at Idss (we know it's Idss because Vgs = 0V). Searching further we see that Idss ranges from 8 to 20mA. It seems they're hiding the critical pieces of information from us. But we can try associating the 4mS value with 8mA, and 8mS with 20mA (Siemens, abbreviated S, replaces the old mho unit for conductance). Comparing with my formula, this gives us two values of n, 80 and 100. (BTW, these values tell us we're not going to get a very high gain, e.g., compared to a BJT, which would have Gm = 0.025 Id, or 320 and 800 mS at 8mA and 20mA collector current.)

These Gm values seem rather low to me, so I poked around, and found a plot of Gm vs Id in a Vishay/Siliconix datasheet. With their data, n = 16 at 1mA, and degrades to 66 at 8mA. The Fairchild datasheet has a plot covering operation at lower currents, with n = 5 at 0.1mA, 16 at 1mA, and 80 at 10mA. So we get a picture of an increase in n and the degradation of 2n5486 transconductance at higher currents. But, oops! now you still need to know the Id current in your circuit. (This is a painful thing about using JFETs, what's Vgs and what's Id, given that they have such a wide range of allowed variation? Well, for a one-off design, you could simply measure the relationship for your specific part.) If you are using zero gate bias, then Id = Idss, which the datasheet says will be between 8 and 20mA. If you measure Id, or use a circuit that sets Id, you'll be closer to being able to accurately calculate your JFET amplifier's gain from John's formula.

--
 Thanks,
    - Win

In article , Winfield Hill wrote: [snip]

[snip]

You are far too trusting about the windows on JFET data sheets Win. There's the device data sheet, and then there's the data sheet for the raw source chip.

Old Mr Cynical here always reckoned that Siliconix did the quickest measurement they could on a chip, (which is Idss), to point raw chips into various device bins and then used each selected Idss range to construct the secondary windows on the device data sheets.

Take that 2N5486, drawn from Siliconix source chip NH.

Selected Idss range is 8-20mA.

The NH chip data says that Vgs(off) will range from -3 to -6.x volts and forward transconductance from about 5800 to 6500 umhos.

The data sheet uses -2 to -6 V and 4000 to 8000 umhos.

Device window MIN = Source chip MIN, minus a bit. Device window MAX = Source chip MAX, plus a bit.

In that way all devices selected for an 8-20mA Idss will automatically be in spec for all the other windows on the data sheet, without having to be measured.

But, and this is the big but, anyone doing the classic JFET sums off the data sheet windows may not get accurate answers.

That NH source chip was used in over a dozen devices, and you can do the same comparison sums on all of them.

I think we've discussed here before: Siliconix Technical Article, TA70-2, "FET Biasing" by James Sherwin. AFAIR now available on the web, but with a different name.

This article gives a good insight into coping with JFET manufacturing spreads.

--
Tony Williams.

I agree completely, and was oversimplifying for purposes of making an easier post.

Bringing back some olde info, here's my post of last year, with your reference from 2004.

TA70-2 ==> Siliconix / Vishay AN102 From an old post by Tony, "AN102 is obviously drawn from the original TA70-2 and seems to be a 1997 update+rewrite in electronic form. The guts of the information given in TA70-2 is still there, relatively unchanged."

You wrote, "first published in Electronics Design in May 1970, then included in the App Notes at the rear of most Siliconix FET data books for the next 15 or 20 years thereafter."

The ED article author was James Sherwin, and you wrote, "a J.S Sherwin is referenced as publishing many other technical articles or tech notes. In no particular order........

"Liberate your FET amplifier". EDN May 1970.

"Distortion in FET amplifiers". Electronics Dec 1966.

"Voltage Controlled Resistors (FET)". Solid State Design Aug 1965.

"How, Why and Where to use FETs". Electronic Design May 1966.

"Knowing the Cause helps cure distortion in FET Amplifiers". Electronics Dec 1966."

--
 Thanks,
    - Win

[...] Vishay supplies the voltage gain as a graph in their JFET data sheets. Gain runs from x60 to x2. Obviously nothing to be proud of, it's nice that it's there though and the same graph can be used with most other JFETS. Indeed, JFET spec' limits are so wide that it seems most JFET circuits can be designed (ha!) using any old data sheet coupled with any old JFET. john

Interesting that jfets have such astounding spreads. I've seen Idss specs over 10:1. I wonder what the physics is here.

Some phemts, compound-semi jfet equivalents, are remarkable consistant. If you do the curves on two parts, the lines are just about on top each other. Precision ion implanting maybe, as opposed to chancy diffusion?

John