Driving PECL

Am 09.12.2014 um 22:43 schrieb Phil Hobbs:

And use 100K, not 10k if you like stable levels vs. temp. Micrel seems to cost less than ON.

regards, Gerhard

You can do CMOS to PECL with just resistors, but you're still starting from single-ended CMOS, with its temperature problems and such. The comparator is diff output and far more stable, and it can slice the true zero crossings from an LC filter after the DDS. You might do a fun differential LC filter directly from one of the DDS diff current outputs, into its comparator, no active parts.

Sounds good. You could lowpass filter the diff output of the EP52, convert to single-ended, and digitize that with a slowish ADC. It's a bang-bang phase comparator, but running at 30 MHz, so you're averaging tons of samples. A little phase noise from the DDS just joins the averaging, so you probably don't need to filter the DDSs super-hard.

I'm guessing your biggest phase error will be in the limiter amp.

PECL is amazingly clean and stable; no Vcc current spikes, essentially no sensitivity to Vcc voltage, super-low TCs, GHz bandwidth. Layout needs to be careful, but just obvious transmission line and termination stuff. Use a solid ground plane and a plane or a big pour for +3.3. Beautiful Hunchback/Brat type folks may not get this stuff, and it can be hard to explain, so I usually do the critical path design myself, as a sketch or routed PADS. I use Appcad and TXLine to calculate trace impedances. Regular FR4 boards work fine for slow stuff like this.

EP52 has internal terminators, which is cool.

Two ADCMP comparators and one EP52 flop does all the critical phase comparison stuff, for about $16. That sounds better than using a lot of mixers and such. Personally, I wouldn't even lay out an alternate circuit.

The single-gate EL and EP parts are really convenient for layout, and much faster than 10/100K.

There are 10EP and 100EP parts, but if you keep the critical signals differential, there's no difference.

Since I only have a few cycles per bit, I was thinking of gating the clock with the FF output, and running that into a counter input on the MCU. The results should be N or 0 almost always.

Yup. Fortunately that's not too hard to calibrate out, because it's

There's a bunch more to the RF handling than I've talked about--I have to generate a 2D acousto-optic scan and then detect a frequency-doubled signal from the TIA, so there are like six frequency conversions involved altogether.

Yeah, but the last ECL thing I used was in about 1985.

Cheers

Phil Hobbs

We both need to do more sanity checks: (0.5 Vrms)**2/50 = 5 mW (+7 dBm), so it's 1.4 V p-p into 50 ohms for a sine wave, or 1 V p-p for a square wave.

Cheers

Phil Hobbs

Yes, that kind of thing causes your space craft to burn up too soon. :)

One reasonable thing to do is run your ECL at ECL voltage levels - between

It's an extra power supply, but since ECL is current-steering logic, the -4 .5V rail is a lot cleaner than the +5V (or +3.3V) rail that's driving your CMOS.

Some of the nicer fast comparators descended from the Am685 required +/-5V rails anyway, so using ECL rather then PECL rails can be helpful there too.

And the 100EP and 100EL parts from from ON-semiconductor have the same prop erly temperature compensated thresholds as 100k.

As John Larkin says, if you are using differential signals (which is a good idea) you don't really care if the thresholds drift with temperature, but my feeling is that you should, anyway. Drifty output levels always find som e way of coming back to bite you.

That John Larkin can notice.

If you use the 100EP and 100EL parts. The 10EP and 10EL is for backwards co mpatibility to 10k parts, so it's not recommended for new designs.

I started using ECL in 1976, and was suing it - off and on - until 1996, wh ich got me into the ECLinPS era.

Once you've got the idea that your traces are transmission lines that have to be routed over ground plane (a -2V plane can be even better) and that yo u have to terminate them with their characteristic impedance, you are fine.

With differential signals you can double terminate - at source and destinat ion - which halves your amplitude (which is okay with balanced signals) but dramatically reduces an reflections.

I got to the point where I was selectively narrowing bits of traces to comp ensate for the (documented) capacitive load presented by an ECLinPS gate. I doubt if it did anything useful, but was a visible exercise in perfectioni sm, of the kind John Larkin would use to impress his customers (if he under stood what was going on).

Correction: the '52 has pulldowns, but not terminations.