divide by 25/16

25/16 is unusual. Usually it's 15/16 or 7/8, etc. Surf on "dual modulus pre-scaler".

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
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I love to cook with wine.      Sometimes I even put it in the food.

doesnt

wich

100.

Thanks, im familiar with dual modulus prescalers but usualy only seen them within PLL chips, I think they divide by either of the 2 ratios one of wich is 1 higher so that a single count can be swallowed by switching to the higher modulus. I found it a bit confusing when I first came accros it, you end up with illegal divide ratios etc.

However I need divide by 25/16 ie 1.5625 not divide by 25 or 16. so im not sure they will work, unless they can replace the /64 prescaler completly.

At the moment Im using a 3ghz PLL chip as a /100 prescaler but needs to be programed each time, shame /100 3ghz prescalers dont seem to be available, I could live with the /64 and work out the real frequency but id rather make it easier.

Colin =^.^=

No, he doesn't want 25 _or_ 16, he wants twenty five sixteenths.

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"Applied Control Theory for Embedded Systems" came out in April.
See details at http://www.wescottdesign.com/actfes/actfes.html

How about dividing by a symmetrical output factor of 25 (1.875 MHz output), and then use a rather modest pll to multiply that frequency by 16.

Although that would give the right output, it would limit the input range by the range of the vco and is probably a bit more complicated, idealy i just want to lose 9 out of every 25 input pulses, hopefully with just a few logic ics.

preferably not to lose all nine one after the other but thats just me being a perfectionist.

Colin =^.^=

I thing his intention is to have sixteen twentyfifths, he wants to "divide by 25/16" or multiply by 16/25

I wonder if the 7497 is available in a fast enough logic family.

I was going to suggest rate multipliers but you beat me to it.

You might have to roll your own out of PECL.

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.

"APR" >>

yes I want sixteen twentyfiths of the input frequency or x 0.64 oh hey hang on but thats the same as dividing by twenty five sixteenths wich is divide by 1.562, so you both right.

25/16 is just the smallest rational fraction.

its what you need to add on to a divide by 64 prescaler to get it to a nice round decimal divide by 100.

Colin =^.^=

range by

just

logic

being

Ah yes rate multipliers, I never realy studied their internal circuit much till now, they always seemed confusing.

the 7497 doesnt seem to be available in any flavour, digikey has some cmos 4000 ones.

how hard can it be to just lose 9 out of 25 pulses. 50mhz shld be doable with the higher speed 74 cmos families I think.

Colin =^.^=

This will fit into a 22V10 so you can do it with one chip if you want.

The dinner bell just rang. I'll be back with something not using programable parts after dinner.

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kensmith@rahul.net   forging knowledge

heh cool enjoy dinner ! ive managed it so far with a divide by 16 counter and a D type flipflop but also quite a lot of gates of different types. maybe I can minimise those down to use just a couple of quad gate chips.

Colin =^.^=

Most swallow systems result in an irregular output waveform, which may or may not create downstream issues (such as unwanted sidebands/spurs). I suspect you have created a problem by your choice of /64. Can you not source some other prescaler? If not, you are probably looking at two cascaded dual modulus divide by 4/5 stages, and I'm not aware of any integrated 4/5 devices.

colin wrote: ...

...

As 25/16 = (5/4)^2, if you follow a 5/4 divider by another one, you'll have 25/16.

-jiw

oo, thats well spotted, so I need 2 circuits that each lose 1 out of 5 pulses. I wonder if that actually works out simpler than 1 that loses 9 out of 25. or did you have something in mind ?

Colin =^.^=

doesnt

wich

100.

may

fortunatly its not a problem, thanks for the headsup tho :)

other

well its a 3ghz+ pecl prescaler, theres not a great deal of choice at 3ghz other than 2^n binary division.

This is cuasing some confusion with the ambigous meaning of the slash, if you mean dual modulus of 4/5 these will divide by 4 or 5, I need to divide by 1.5625 (=25/16 as a fraction) wich doesnt lend itself to dual modulus. well actually a dual modulus of 2/1 is ok!

Colin =^.^=

You need to think about this carefully, as another poster mentoined, what you will get is an irregular pulse train, actually a signal that jumps back and forth beteen two frequencies that average out to your desired frequency but is never actually equal to your desired frequency. If this is OK for your application, then go for it, in many cases this is not OK.

Mark

Ok I'm back from dinner :>

If you write out the numbers from 0 to 25 in base 5, you will discover that the lower digit is odd 10 times. Just looking at the LSB of the counter, you could skip 10 clock pulses.

When the upper digit is 4, you could allow one clock for one of the odd numbers

LSB A -------------------------! \\ !NAND >------- Allow clock B --------------! \\ --! / !NAND >-- C -- -----! / ! .. etc .. ! ! MSB H---------

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kensmith@rahul.net   forging knowledge

In article , colin wrote: [...]

Rate multipliers are easy to understand if you start with the idea of making a very bad one and then improve it like this.

Given a binary counter and a binary comparitor, you can allow the clock to come out until the number in the counter hits some value and then block the count until the counter overflows.

This gives a very bursty output.

Now rewire the counter swapping the order of the bits so that the LSB is hooked to the MSB of the comparitor and so on. Observe how that spreads out the pulses.

This is how I first got ahold of how they work.

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kensmith@rahul.net   forging knowledge