Dirt Cheap 2% Full Temperature Accurate Clock Needed

an be anything from 1MHz to 48MHz

or and adding a couple of opamps to the ASIC to pay for the die and package , I need the opamp anyway

floor, so that does really not add cost?

Sometimes life spans out nicely. Yesterday I was in the middle of a design where the drift of the mcu oscillator posed a problem. Today I met with the FAE for the product, he disclosed a new part coming out, with very good pr ecision oscillator (1% full temperature range), and behold, he could also r educe the cost of the device in the first place :-)

Cheers

Klaus

It can't _unless_ you add one more inverter AND the R/C juncture has NO ESD diodes... a risk. ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| STV, Queen Creek, AZ 85142    Skype: skypeanalog |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 

     Thinking outside the box... producing elegant solutions. 

"It is not in doing what you like, but in liking what you do that 
is the secret of happiness."  -James Barrie

The pick-and-place costs alone argue against the quartz crystal and capacitors. The resonator is a clear winner (but, the price target is VERY low ). It might just boil down to how competitive the suppliers are.

I guess one of us must be out of touch with reality.

--sp

--
Best regards,  
Spehro Pefhany

e:

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a

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ega328pb_datasheet.pdf

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IIRC (probably not or you would have thought of it - maybe I am thinking= =

of a pic) the chip can sense it's internal temperature, it has an =

oscillator tune register and an eeprom. What is wrong with temp =

calibration via the ossc tune function and saving the result in eeprom?

-- =

Using Opera's mail client:

can be anything from 1MHz to 48MHz

ator and adding a couple of opamps to the ASIC to pay for the die and packa ge, I need the opamp anyway

se floor, so that does really not add cost?

s

y T s

where the drift of the mcu oscillator posed a problem. Today I met with th e FAE for the product, he disclosed a new part coming out, with very good p recision oscillator (1% full temperature range), and behold, he could also reduce the cost of the device in the first place :-)

The trouble with electronics is that you have to keep coping with new parts . The good part is that they tend to be better or cheaper than the parts th ey replace, and quite often both.

--
Bill Sloman, Sydney

Spehro, would it be possible for you to let me know your part number, then I will ask for a qoute. That would be a very interesting exercise for me (alternatively by private mail)

Cheers

Klaus

The ESD diodes are insignificant to timing if R1 >> Rt, as indicated in the ASCII circuit you snipped.

Some Google-fu brings up the original app-notes in this 175M monster PDF:

See ICAN-6267, pg. 531, for the astable.

ICAN-6230 Fig. 4, pg. 519 and appendices B/C make a spirited but not especially compelling case for using the CD4047A for its special input ESD network, in order to eliminate the need for R1 and avoid its minuscule timing effect.

ICAN-6230 is independently available here, as a 400K PDF:

Cheers, James Arthur

"Insignificant" as in the whole deal

Then you'll be able to confirm that Table II. shows that, at Vdd=6V, none of their astable test oscillators drifted more than 1% over -55C to +105C.

Doesn't have to. The OP assumed initial calibration (trimming).

Cheers, James Arthur

Papers do not truth make. Having been around the barn for many years I'm cautious... AND experienced. But, hey, go for it. I love it when people ignore my advice then come begging for me to "fix" their problem >:-}

That only eliminates "P".

...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| STV, Queen Creek, AZ 85142    Skype: skypeanalog |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 

     Thinking outside the box... producing elegant solutions. 

"It is not in doing what you like, but in liking what you do that 
is the secret of happiness."  -James Barrie

Just ask for a generic SMT HC49 crystal tape and reel. Price should meet your limit (< CNY 0.2)

--sp

I won't be begging for anything--ICYMI, it's not my problem. It's Klaus', and he's already solved it.

I was merely providing a reference. If you'd like to show their result is flawed mathematically, go for it.

My suggestion was to use a comparator for U1a, virtually eliminating both the threshold uncertainty & drift.

Cheers, James Arthur

It would take building it up in Spice, then running it over all PVT corners, but since "It's Klaus' [problem], and he's already solved it.">

So, since it's "solved", I'll let it go.

Indeed, but that's not the same as the inverter style. A 555 timer (in essence comparator style, with VDD compensation) is actually quite good, but not at higher frequencies.

The there's the effect of the delay of each of the elements which will rear its ugly head at high frequencies >:-} ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| STV, Queen Creek, AZ 85142    Skype: skypeanalog |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 

     Thinking outside the box... producing elegant solutions. 

"It is not in doing what you like, but in liking what you do that 
is the secret of happiness."  -James Barrie

I worked out df/d(Vth), just for fun. Here's the 'plot.' (Assumes R1 >> Rt.)

Vdd=5V Rt=4.7k, Ct=100pF (Vth = threshold voltage)

Vth Rt (k) Ct (pF) t (uS) f (Hz) drift 2 4.7 100 1.04979 952,573.0 -1.6%

2.1 4.7 100 1.04355 958,271.6 -1.0% 2.2 4.7 100 1.03876 962,686.1 -0.6% 2.3 4.7 100 1.03538 965,830.0 -0.3% 2.4 4.7 100 1.03336 967,712.7 -0.1% 2.5 4.7 100 1.0327 968,339.6 -- 2.6 4.7 100 1.03336 967,712.7 -0.1% 2.7 4.7 100 1.03538 965,830.0 -0.3% 2.8 4.7 100 1.03876 962,686.1 -0.6% 2.9 4.7 100 1.04355 958,271.6 -1.0% 3 4.7 100 1.04979 952,573.0 -1.6%

Cheers, James Arthur

That's just Vth. How about stage delays?

External R and C? Or on-chip R and C? ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| STV, Queen Creek, AZ 85142    Skype: skypeanalog |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 

     Thinking outside the box... producing elegant solutions. 

"It is not in doing what you like, but in liking what you do that 
is the secret of happiness."  -James Barrie

External RC, obviously. I'm not designing Klaus a chip!

I just derived the exponential equations, then made a spreadsheet of the function. The oscillator's period works out to:

Vdd - Vth^2 period = -RC ln( -------------------- ) 2Vdd^2 + VddVth - Vth^2

Cheers, James Arthur

Simulating a real CMOS circuit (inverters, I've done this exercise many times before :-), I get +/- 3.5% (1MHz).

I don't have a breakdown of what it's due to, Vth, versus stage delays, just the whole enchilada.

A sturdily designed comparator would minimize the Vth issue but exacerbate the delay. There are even ways to minimize the delay effects, but it takes an extra resistor and an extra pin (I've linearized wide-range VCO's this way). ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| STV, Queen Creek, AZ 85142    Skype: skypeanalog |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 

     Thinking outside the box... producing elegant solutions. 

"It is not in doing what you like, but in liking what you do that 
is the secret of happiness."  -James Barrie

Drift, or absolute accuracy?

The comparator only need stabilize the d.c. threshold; it can be outside the oscillator's a.c. loop.

As you can see from my table, d(f)/d(Vth) is minimized in the vicinity of Vth=Vdd/2. For that reason, fixing Vth precisely at Vdd/2 is a big win.

On a chip I'd think Vdd drift could be compensated with extra circuitry, but absolute accuracy would be tough--I guess that's why they use EEPROM trims.

Cheers, James Arthur