Decoupling Tiny/LittleLogic,,,

[snip]

The thing that worries me is not the purity of the capacitance of the power/ground planes - it's the via+ball inductance. Fortunately, for each nasty supply there are normally numerous vias connecting to the planes that will reduce these bad effects. I would really like to know if the Altera and Xilinx FPGA on-package decoupling caps are really the ones saving our butts.

If you really are a moral person you will invent a way to easily probe the dV/dt at the silicon. Some type of non-intrusive technique (using neutrinos?) would be preferred. The whole world is watching, John.

Bob

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This reminds me one thing in my past. In design review meetings, I used to suggest that once we confirm basic operation of the board we would start taking caps little by little off the pcb until we start seeing problems, and then adding some caps back into the board, and supposedly we just achieved the optimum bypassing. How many more extra caps I should add back is the key here, obviously. To my frustration, once a new board worked they wouldn't give me time to excersize this sort of things.

Atsunori

That's pretty funny. We do the same things in our design review. "We'll cost reduce it later". Yeah, right. It NEVER happens.

The problem with my designs that include FPGAs is that I never know what type of new code will be loaded (in the field). I guess the thing to do would be to create a test load that has every single flop toggling at its max frequency. Oh, wait. I don't thing that the FPGA suppliers recommend this type of operation. I think they've said it would destroy their parts. Oh well. I'll figure it out LATER.

Bob

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utts.

One of the problem with this scheme is you don't know if the DUT is hot, slow, or on target. So you put in enough bypass for maybe a typical chip, but then the vendor produces one that is hot (fast) and the noise increases due to faster switching.

Just the other day I needed a miliohmmeter to check a power transformer secondary. I grabbed an LM317 and 1.2 ohm resistor to make a 1.024A (as measured) CCS. Now, my load wasn't exactly typical, as a transformer has considerable inductance, but nonetheless it oscillated audibly. Since speed was no concern, I put 0.47uF caps on the input and output as usual, which quieted it down nicely.

Tim

--
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Could be. But a via doesn't have a lot of L, and there are usually a lot of them in parallel. A bypass cap inside the chip doesn't help signal-current ground bounce and may make it worse.

I'm sure the semi folks can probe exposed chips up into the 30 GHz range. The probes and scopes are available for some reasonable fraction of a megabuck.

Actually, if a chip has a lot of ground or Vcc balls that are known to be in parallel inside the chip, one of each could be sacrificed, brought to tiny surfmount coax connectors during PCB layout, as Kelvin probes. How's that, Whole World?

But we've had no ground/bypass problems with BGA FPGAs so far. Has anyone else had problems they can blame on bad grounding or bypassing on FPGAs?

Interestingly, we've had zero soldering problems, too.

John

I know one guy who doesn't use bypass caps at all, and his stuff works.

John

If an FPGA is clocked at a constant rate, it will ususlly pull pretty steady average (low frequency) supply currents. If the clock varies, or some powerdown tricks are used, it can go from milliamps to amps instantly, like a Pentium. Then your power supply/bypass system has to be very stiff for instantaneous load changes, not merely nanosecond spikes at a constant rate.

You can get similar effects from driving wide terminated busses with interesting data patterns. Some LDO or switcher regs, with a pile of ceramic bypasses, will ring on load steps.

John

Abby Normal?

Are you referring to Young Frankenstein with Marty Feldman... and Frau Blucher?

Get the Sedagive...

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Electronic Kits for Education and Fun

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

I've seen a few in Virtex-E but only only associated with wide (e.g. 64 bit) buses of single ended I/O like SSTL or HSTL. (This is where I learned that BIST using random patterns may not pick up all faults. Alternating all ones and all zeros is sometimes required.)

I saw another problem that related to insufficient decoupling on the Vref (for an HSTL clock input) that caused a DLL to unlock. This was fixed by moving a cap a few mm. Here's the c.a.fpga thread from 2000:

That one was Virtex-E as well. I haven't seen a similar problem since then. Presumably the contemporary pinouts, BGA designs and internal caps are much better. Maybe it's just that I learned from the experience and don't use single ended I/O these days?

(I should point out that these faults were not in my circuits or layouts, and not in my current job.)

Regards, Allan

Yep ;-)

...Jim Thompson

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| 1962 | I love to cook with wine Sometimes I even put it in the food

The simultaneous switching output (SSO) limitations on anything earlier than Virtex 4 is pretty limited. That's why, in V4, they introduced their 'sparse chevron' BGA ball patterns (were the older ones referred to as 'dense shell'?). The internal loop inductances were really reduced with this pattern, and thus the so-called ground bounce (and power bounce) effects were reduced.

SSTL and HSTL are nasty - especially when you've got a bunch of outputs simultaneously switching from 1's to 0's. At the company I used to work at, we called this the "killer pattern". Random data -- no problem. 128 bits of I/O switching from all ones to all zeros -- ERROR! Differential standards like LVDS sure make it a breeze to accomplish the same thing (at the expense of twice as many I/Os).

Bob

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...

Hope This Helps! Rich

Even if you don't expect any transients from other components "on board", try this test. Put an operating Nextel Iden phone next to your prototype and you might be surprised. Its a good idea to bypass your chips! You might find your inputs susceptible.

Also worry about ESD. I build a prototype microchip project and neglected to install proper pull ups to unused pins because I "understood" there were internal ones. I put this circuit over a plastic cutting board I was using as work surface. The tiny amount of static electricity (here in humid Florida)caused the chip to reset at odd times giving erratic performance.

--
Joe Leikhim K4SAT
"The RFI-EMI-GUY"©

"Use only Genuine Interocitor Parts" Tom Servo  ;-P

One of the popular hobbyist magazines provides circuits on request to readers. I have never once seen bypass capacitors included in the designs provided by the authors. I have to wonder how many readers were disappointed when relays chattered or the circuits otherwise failed to work.

--
Joe Leikhim K4SAT
"The RFI-EMI-GUY"©

"Use only Genuine Interocitor Parts" Tom Servo  ;-P

Abbey Somebody , one of dimbulb's moronic 'nyms, as well.

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