Decoupling Tiny/LittleLogic,,,

It all depends on the operating frequency of those devices, as well as the way your PCB is constructed. If you are using them for driving LED's or relay control circuits, you don't really need bypass caps at all. Can you tell us how you are going to use those Tiny/LittleLogic's?

Atsunori

It is good practice to decouple all digital logic with 100nF ceramic as close to the Vcc pin as possible. It is also advisable to have a larger tant somewhere on the line, depending on how smooth you want the rail to be.

Looking at the rise time of the Little Logic device, it is 2.5ns when driving into a 50pF load. If you transit from 0V to 5V in this time, from

i = Cdv/dt

this implies a current of 50E-12 x 5/(2.5ns) = 100mA.

It depends on the impedance of your supply rail, but with 100mA surges going into the logic device every time it switches, I would want to decouple it...

Hope this helps

--
Bill Naylor
www.electronworks.co.uk
Electronics Kits for Education and Fun


 wrote in message 
news:ae2c2cc5-04d3-418a-9425-f44c98fdfcd4@z7g2000vbh.googlegroups.com...
> Hi,
>
> When using traditional, say 74HCTxxx, logic we are taught to decouple
> every chip near the power pins...
>
> What about Tiny/LittleLogic? Should they be decoupled per chip too?
>
> Thanks
>
> "A novice"

I'm not sure that is entirely safe. Those parts have very fast transition times and can generate a big fast current spike when switching. I could easily believe such parts would oscillate given a poor layout. Certainly they could disrupt a poorly bypassed supply rail.

--

John Devereux

Also, if the logic contains storage (flip-flops or cross-connected gates or whatever) a glitch could change the state of the circuit.

If you're doing a multilayer board with ground and power planes, just a few caps scattered here and there will be fine.

Most of the Tiny families are very fast, so at least a solid or near-solid ground plane is a good idea. If power is distributed by traces, and not by a good plane pour, yes, a cap per chip, close to Vcc and connected hard to the ground plane, is prudent.

Two chips can share a cap if the Vcc pins are very close and the power traces are fat.

If the logic is static and you don't mind nanosecond glitches, driving leds or relays maybe, anything will work.

Most of the Tiny Logic is so fast that, if you're doing clocked logic, transmission-line effects are serious, even at low clock frequencies. Use the slower parts if possible.

John

That means, in that partucular circuit application you mentioned the TinyLogic circuit itself or following stage is sensitive enough to supply rail inductance/impedance or to the transitional output from the TinyLogic. If that is the case you need bypass caps physically close to them. In many other instances,

(1) Your PCB supply rail impedance around the TinyLogic is already low enough due to bypass caps for other parts on the PCB. (2) Your TinyLogic circuit is insensitive to the supply rail impedance/noise. (3) The following circut driven by the TinyLogic output is insensitive to fast transitional output from it.

It depends on your application. In my case, (1) is probably the majority of the case. Though, some designers that I work with tend to through in bypass caps for every supply pin and part automatically.

Atsunori

I saw one pcb being assembled, on an automatic p+p machine, that had over 3000 bypass caps!

John

I have learned my lesson the hard way:

Designing charge pump circuits - you would think this predominantly analogue component would be immune from noise - not the case - a 100nF was needed close to the Vcc pin to bring the switching frequency into spec

Temperature circuits: single chip temperature sensors will give a reading that is 'too cool' unless decoupled with a 100nF close to the pin

7805 regulators: this bullet proof, age old, lifelong friend of a component can still misbehave if you do not decouple the INPUT. I thought I had a rock solid input so did not bother with decoupling - it gave 5.00V output. 2 weeks later, my 7805 5V regulator was outputting 6V and cooking everything downstream of it. There was significant ac content on the input that disappeared with a 1uF decoupling cap.

If you do not decouple, then your circuit could misbehave for the most bizarre reasons and you'll look everywhere except at the supply rail for the solution. You do not deserve that amount of grief!

Hope this helps

-- Bill Naylor

Electronics Kits for Education and Fun

Was it designed by Sun Microsystems? :-)

FPGA venders insist that I provide bypass caps for every single supply pin and ground pair for their chips. I think they are teamed up with those ceramic capacitor manufacturers.

Atsunori

Anritsu, a huge board, part of a RAM tester machine. It was being assembled in a little tin-roof sort of garage, in Hamamatsu, jammed fill of quarter-megabuck Panasonic turret-gun assembly machines.

John

Actually, yes. Some suggest more than one cap per supply pin, a big cap and a smaller one, sometimes even three! Insane.

We use four caps per supply rail per FPGA, 12 total for a Spartan3, and that's probably overkill paranoia.

John

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Regarding the charge pump, it has a relaxation (sawtooth or trianble) oscillator, which is essentially an analog circuit. The charge pump has to deal with switching noise from the power fets that is synchronous to the state change of the oscillator, so this is a classic case where bypass is needed. Lastly, some of those designs use body snatchers, which might behave poorly if the substrate is bouncing around.

What's a body snatcher?

John

You never heard of the "Abby Normal" episode ?:-)

...Jim Thompson

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The paranoia is well founded because it's difficult to know what the maximum dI/dt is going to be into each FPGA pin. External caps mean high series inductances and thus pretty hefty voltage drops at big dI/dt. This is certainly why Xilinx and Altera provide on-chip decoupling on some of their devices.

If you've got HSPICE, all the models, and the time to do the simulation then perhaps you can be *sure*. For the other 99.999% of us it means almost certain overkill on the number of bypass caps used.

Bob

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The presence of big, closely-spaced power and ground planes changes the game entirely. The plane capacitance handles the fast stuff, so the caps don't matter as much. And the planes are not very susceptible to modeling, especially with Spice.

John

The super thin dielectrics now avaliable certainly help. But how good is good enough?

Is the net series inductance to the nearest perfect capacitor around a nanohenry? 0.5nH? 0.1nH? Is the max dI/dt in the range of 1A/ns? 0.5A/ns?

0.1A/ns? How close are we getting to the lower limits of our 0.9V supply at the FPGA silicon? I don't know.

What I do know is that keeping a bunch of 0402 0.01uF X7R caps on the back side of the pcb for the large/full/highly-clocked FPGA and using 2 mil ZBC dielectric between the power and ground planes *seems* to work. But how much margin do we have? Perhaps it's best not to think too much about it. We do need our sleep.

Bob

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Maybe it isn't as generic of a term as I thought. A body snatcher is when you move the body (or well if you prefer) with fets rather than hard wire it to a power supply. You would use the term if the well can be connected (snatched) to different potentials with fets. However, two source coupled N-fets in a p-well that go to the common source wouldn't be considered snatched, but rather floated.