Debouncing....at About 1Mhz

QED ;-)

...Jim Thompson

-- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | |

So you've been converted to the Bob Pease school of hand waving ?:-)

My POV: Design puts the idea onto paper. Simulation proves that what is on the paper really works. But simulators don't "design". In my business, simulation "proof" is required for each and every process corner, otherwise the customer doesn't "buy".

...Jim Thompson

Your Sysreset sets Q high, but your sim starts with Q low. Why?

John

The default set-ups included FF initial conditions Q=0. If I uncheck that box it starts, as would be expected, with Q=1.

...Jim Thompson

Well, run that. It's more interesting.

John

Yep. It takes one cycle for the output to be correct.

...Jim Thompson

It seems to work, but it's awfully convoluted. It would be, for me, like one of those things that I designed but that I can barely understand myself; there are too many possible states, and the dflop clock sometimes comes from the input, and sometimes comes from the input xored with the internal delay. And the input can chatter, or it could be a single edge of either polarity. All those conditions have to be proven to work, and proving it is too much work.

I avoid clever stuff like that, in hardware and in software. Sorry, but I prefer my first circuit, because it's a lot easier to understand.

John

Yup.... :) I've been thinking about the posted schematics. It's a little overwhelming..

Here's a rough model of a JL based cct. without the RC. This was described by myself in a prior post. Jim also saw this coming.

I'm 'painting' now :) with another JL inspired design (the one with the front end differentiator). If all goes well .. It's 2 devices from 2 IC's.

Will post soon it's not too gibberish :)

D from BC

I still find it amazing that after benchtesting, I can see that I forgot to include parasitics in a circuit model. After including the parasitics in the model, I get the sim waveforms that I see on the scope :)

Bouncing between model and bench and model and bench can build a good model.

D from BC

Forgetting the parasitic aspects of circuit configurations as well as the individual components themselves is the main reason why those that do not like simulators hate to use them. They fail at doing so.

A good sim will match the real circuit just about exactly. Considering the elements of the software used to make a sim a sim, it would have to.

It's like Ohm's Law. The rules are the rules, and if you are following them, your calculator will display the proper figure in its mantissa.

Sims work great. I love 'em. When they don't match the real data gathered, and the engineer goes about the chore of finding out why, he should also increase his education in the field as a result. A proper sim will always match the real data. If it doesn't, something was left out. It is like a puzzle.

An asynchronous circuit like this, and even moreso some of the others that gave been posted, has internal delays and is subject to all possible timings in the chatter zone. Spice can't really test all the possible combinations of timings. You can generate a chatter simulator, but you can't be sure its deterministic behavior represents the real world of arbitrary timings. Complex async circuits can have low-probability picosecond-wide windows of hazard.

John

You've posted the hazards of asynch..ummmm..I'd say 5x. Now that persistence. :)

D from BC

I got inspired by that differentiator + schmitt invertor sketch of yours. The idea was to move the signal into the hysteresis levels. I though I'd try doing the opposite..Moving the hystersis levels to meet the signal..

Check out my hysteretic hairball! :O *

Notes:

• Top wave is the inverting input of U1. (It's a cool waveform. 4 levels! :) )
• Prop delay is from a single device at less than 10nS.
• This can be a 1 chip solution with a fast dual comparator.
• I picked the LT1713 just because it's fast.
• The integrator + U2 could be replaced by some 'one shot' IC solution
• This circuit is not quite baked because I skipped on the math and did best guesses on the resistor values.

With some tweaking, I think this might be a good circuit.

D from BC

Think of the XOR as a device that is switched from being an inverter to being a buffer. The switching does not occur while clock (input) edges are present.

Does nothing after the first transition... it's an edge-triggered flop.

When I feel confused I drinks a glass of wine ;-)

...Jim Thompson

It took me MANY years to trust simulators. Initially even bipolar device models were bad.

But I still "design" by first "sketching", even if the "sketching" does use a schematic capture program... I'm faster that way, no erasing... drag stuff around... such fun!

Then I simulate.

...Jim Thompson