DDS, again

On Linux, we have 'sox' that can convert between time-value pairs and .wav in either direction. I suppose there must be a Windows version. I suspect the piecewise-linear problem will still be there.

As for the convergence problems: LTspice doesn't like discontinuities. Jim Thompson approximated everything with smooth functions. His favourite was tanh.

Jeroen Belleman

LT will input a binary .wav file without the piecewise thing, I think, but I didn't want to add the conversion step. Or learn yet another program. And I sure didn't want to write the PowerBasic code to make a .wav file.

The irony is that after some nontrivial amount of coding, I think I'll just use the MSB of my 40 MHz 32-bit phase accumulator as our waveform clock. Nobody important will notice the jitter.

The "RF" mindset, that one has to do the sine and dac and hi-rent lowpass filter and comparator, is not only a bunch of work and expense, it gets really nasty at low frequencies.

Oh well, the project was educational and will probably be useful some other day, when clock purity matters more.

It would be interesting to try to stay all on-chip in the FPGA, to digitally filter the MSBs of my 40 MHz NCO with some digital filter running on a faster clock.

My guys say that they could run the phase accumulator at at least 100 MHz in an Efinix FPGA, and that offers ideas too.

Tanh is indeed slick. I have some logical statements in my LT Spice NCO that it may not like.

I think you have the funds to buy Cadence Pspice. It has auto convergence build in. It's seldom I see problems with convergence after they added that feature.

LT Spice is usually pretty good. It just didn't like my trying to make a 32-bit phase accumulator with an analog circuit.

I once fixed a convergence problem by adding one resistor to the circuit. 1K, one ended grounded, the other end open.

LT is horrible with digital stuff. Imagine making a 32-bit phase accumulator with its parts. There isn't a screen big enough.

Qspice is I hear better at mixed-signal sims.

I can always have one of my kids Matlab the hard stuff.

Given a 40 MHz phase accumulator, one could spin up a clock at some mutiple, 160 MHz maybe, and fake the dac/lowpass/comparator thing to reduce jitter.

I think it's just a lookup table on some MSBs of the 40 MHz phase accumulator. Of course the new fake DDS clock output would be quantized to the 160 MHz clock domain. Maybe.

If you buy Pspice Advanced, you can run c++ code in each time step, or whatever timestep you like. I am doing that to simulate a digital SMPS in spice

qspice and also run c++ or verilog modules

The whole point about DDS frequency synthesis scheme is that it isn't limited to the master clock edges.

The sine-look-up table gives you a staircase approximation to the desired sine wave, which is limited in just that way, but as soon as you low-pass filter the staircase steps into a smooth slope, your zero-crossings can move smoothly and continuously.

Faking that stage is - at least in theory - doable, but it's going to be messier than the DAC-low-pass filter scheme, which has the advantage of being popular (so that there are lots of standard parts available) and easier to explain.

Then don't do it at low frequencies. Do it at 2^N times the low frequency that you want, and then after the comparator divide by 2^N.

I think that can be done, but very carefully. We need long-term phase coherence to simulate a complex geared machine, and we need frequency changes to happen at a selected phase angle, like top-dead-center of some waveform of some part of a mechanism.

Using the MSB of the phase accumulator is sure appealing. Going off-chip to a DAC and a filter and a comparator adds time lag and jitter.

Most DDSs are RF oriented so don't care about time. Maybe some exotic radars would.

Big radars in general care about time and phase a lot, not to mention phase noise. And long-term stability over time.

Joe Gwinn