DDS follies

I tried doing some waveform generation by something like this method in an ICE40 FPGA, creating a 10.7 MHz IF signal for an FM-stereo alignment generator. As I recall I used three output pins, and a very simple resistor DAC.

The result was a nasty-looking waveform, with some serious switching glitches at some transitions between values. There was enough difference in signal-propagation time between the pins and the driving gates to cause some race conditions, leading to a short high-value spike during the transition.

Even putting the pins into registered-output mode didn't help very much... the register-being-clocked-to-pin-transition delays weren't constant. I think I was just asking a low-end FPGA to do things it wasn't really designed to do.

It would have taken multiple filter stages to get rid of this. Using Schmitt comparators (such as you suggest) would have gotten rid of the glitches (assuming that board and part parasitics didn't let them bleed through) but then I'd have had to low-pass filter the comparator output again to get something like a sinewave.

One possible way around this problem would be to arrange the outputs to operate as a Gray code (or similar), so that one can guarantee only a single pin transition per clock. I imagine there's probably an R-type DAC topology which could support this, but I haven't worked with one personally.

We use home-made 1-bit delta-sigma DACs sometimes. Just an RC out of an FPGA pin. That's good for slow stuff like an offset trim or tuning a VCXO or whatever. It's a bit better than PWM but it's still crazy slow.

I'm guessing that a 1-bit DDS, just filtering the MSB of the sine lookup table, would be awful too. But imagine a 65K x 1 bit sine lookup!

Hmmm, that makes a square wave: Out = In. Never mind. [1]

I trekked down the hill to retrieve my DDS book and my treasured "Signals and Systems for Dummies" paperback. So I can snoop a little theory now.

I might simulate some cases, filter and all, but LT Spice is impressively klutzy at digital stuff.

Here's a past attempt. Instead of drawing a zillion flops and gates, I faked an analog phase accumulator.

In the radar world, we use two-stage DDSs implemented in a big FPGA. The first stage generates the phase increment, the second generates a phase slope by cyclic accumulation of phase increments, rolling over once per full cycle. The resulting phase sawtooth is fed to either a lookup table or a CORDIC module of some kind. There are thousands of variations. The reason for two stages is to create perhaps non-linear frequency chirps.

Analog Devices used to have a guide to DDS principles, from which to get ideas. Then implement only what is needed in a FPGA. Unless you are going for very precise sinewaves, the lookup table need not be all that large.

Joe Gwinn

afaict the AD9830 is just a phase accumulator and a lookup table, you should be able to do that quite a bit faster than 40MHz in an FPGA

It might be possible to use some deserialiser DDR trickery to place edges between the main clock edges

you could try Qspice, you can use verilog models in that

but it would be easier to do in matlab,octave, python, basic, c whatever

or just run verilog in a simulator

LT Spice refuses to cooperate. It gets jealous when I am too clever at fooling it, and stalls or throws errors on random modes.

Now I'm doing the DDS math in PowerBasic and making .WAV files, and letting LT import them for post filtering and plotting and FFTs.

I've just about decided that the academics and RF s-param boys have over-complicated the DDS situation. If all I need is a digital clock, I don't much care about all those radio things.

I have to make the 32-bit DDS look like it has a 40 MHz clock, for compatibility with older products.

So why have sine tables and DACs and filters and comparators? Why not use the MSB of the phase accumulator as my system clock? I can synthesize one octave and divide down below that.

It might be possible to spin a faster clock and make a digital filter, esentially, lowpass the accumulator triangle waveform to reduce jitter; too much work.

I can't see the virtue of a sine lookup. The phase accumulator makes a triangle and, near the zero crossing, a sine wave looks just like a triangle. Well, it's 2*pi steeper, but a zero crossing comparator isn't impressed by that.

Why take a perfectly beautiful triangle and spin the poor thing all around in a circle?

Am 07.12.24 um 00:01 schrieb john larkin:

I published a DDS maybe 15 years ago. It ran at CLK = 230 MHz including sine table in a Spartan-6 on a SP605 eval board. If you don't want the sine table, leave it away. That won't make it slower :-) It is pure VHDL, no Matlab or Xilinx macros.

The number of pipeline stages (0..10) and resolution can be set by a constant, output width(s)is taken automagically by the buses that are connected. The sine ROM has only 90°, mirroring etc included. sin/cos outputs are available at the same time yet do not need another ROM.

I needed it for an all-digital PLL, so a Cordic with it's long delays was not an option.

cheers, Gerhard

Was that for an RF application? My feeling is that a programmable-frequency digital clock doesn't care about a lot of RF virtues. Most all that matters to us is jitter.

We're simulating rotating machines which are shaking and bending and howling anyhow. Maybe we should add programmable jitter as a feature!

We do care about latency of a frequency change, but nobody would notice a microsecond. Users will program many channels of new frequencty and strobe install all atomically.

I can sort of see why one wants a sine table to make a really good RF synth that pushes the Nyquist limits, but that's not our problem now. An FIR lowpass filter, after the DAC, reaches out infininitely in both directions, so shouldn't be allowed to see any gnarly edges or anything any time in history.

Surely you mean an IIR filter... FIR filters don't know about anything about what happens beyond the limits of their coefficient table.

John

Sorry, IIR, like the analog filter in a typical DDS.

I guess one could do either type, digitally, in an FPGA, to smooth out the gross steps of some number of MSBs of the phase accumulator. One might PLL up some clock to make a really fast digital filter.

But the result would be in the new, faster clock domain.

Luckily we have almost a year to redesign a product, before we run out of parts, so we can think in various goofy directions for a while.

A fast-clocked FIR transversal filter might be interesting. If my phase accum clock is 40 MHz, a FIR filter could span some integral multiple of 25 ns, something like that.

Triangular waves are just integrated square waves and they have all the odd harmonics until you run out of switching speed.

The amplitudes of the higher harmonics drop with the square of the harmonic number for a triangular wave, so they are less offensive than square waves. but they are still there.