Cree Mount wire to board

phone companies use wire wrap- it's extremely reliable, fairly dense and easy to work with. Here the complains seem to be it's bad for > audio signals speeds, which is likely true, but backplanes of mainframes was not the primary use of wirewrap.

Saying it's bad for frequencies above audio is not a very good characterization. I've seen backplanes running with 25 MHz clocks that used wirewrap. But that was about the limit. Even at 25 MHz the reflections could get a bit hairy. Of course it is the edge rise/fall times that are the problem, but you can't have faster clocks with slow edge rates. At slower clock speeds the edge rates could still be fast and that can cause double clocking. So the clock signals need to be carefully handled. In the ST100 with 25 MHz clocks, they were distributed with twisted pair which preserved the edges pretty well. I don't recall if they were single ended TTL or differential ECL as the machine contained both types of logic.

About the same time clock speeds rose much above 25 MHz the density of the chips rose so that a lot of functionality could be integrated onto a single board obliviating the need for back planes all together in many applications. I want to say the Intel i486DX2 chip used a slower speed bus clock than the internal clock. That's when the real fun started with all the really fast stuff on chip even keeping the circuit board from needing to deal with significant SI issues, at least for a while. I seem to recall once the memory interface got up to 100 MHz or so the interface had to be designed very well to deal with SI issues. Many weren't. That's where all the mythology of who made "good" memory chips and modules. The reality was the poor board level bus design was being dealt with by swapping individual memory modules.

I wouldn't worry too much about the thoughts of a person that styles themself "cydrome leader".

I doubt they would be interest to have their concepts challenged by something like the 32-bid Modcomp IV minicomputers, which were wire wrapped TTL and had an instruction time of 160ns.

That were ordinary PC/AT floppies with just one sector destroyed. The original distribution disk had to be in drive a: and before they would write any results to the hard disk, they would write the floppy sector that was defective. If they read the sector back and the data was OK, it must have been an ordinary disk that someone had copied. The defective sector would never return the correct result.

The laser was just to impress with hi-tech. A needle would have worked just as good. Needs a steady hand and some booze.

Having to rely on a floppy disk that might fail completely and that then would have to be replaced by mail from RACAL was not the way to a happy customer relationship. Or having to store the disk overnight in a safe.

cheers, Gerhard

I've done a signal averager in risetime-controlled 100K-ECL with 200 MHz clock. The clock was distributed in semi-rigid cable, the rest in WW on a special ECL multilayer board made by Augat, and the ww pins were directly in the huge board, like a 2000 pin socket. The board did cost a few grand.

It worked nicely, but in the end the winner was some CMOS FPGAs with 8 data streams in parallel. There was a ECL/CMOS stream splitter/demux chip from Siemens. It was just like specially created for this job.

cheers, Gerhard

Tom Gardner snipped-for-privacy@blueyonder.co.uk> wrote in news:shchsm$t21$ snipped-for-privacy@dont-email.me:

Hahahah... and then they said... "Slow Slew me."