Cree SiC fet model problem

Link to the model? ...Jim Thompson

Is it really so hard to remove the two extra node callouts from the .SUBCKT statement, and add

VTC TC 0 {TEMP} VTJ TJ 0 {TEMP}

anywhere in the body? *shrug*

Tim

Here's their model

and my test case

and it needs this:

to make the LT Spice schematic symbol.

The separate power computer + lowpass filter is easy, but the model is annoying. I've seen complaints about its guts, too. What's your opinion?

An ST part has a model with similar Tc and Tj pins, and they have an appnote that actually explains it! You are supposed to add external RCs to simulate thermal time constants. Or something. It still violates conservation of energy.

I'm trying to reconcile my first-article HV pulse generator with the simulations.

Nasty. It'd have been nice if they could have at least grouped all the Tj/Tc stuff into a single module.

That's what happens when you let PhD's with nothing but school-book experience write models.

I'm currently trying to fix a Microchip model that barely runs on PSpice and hangs on LTspice... it has _25_ TABLE statements... the "PhD's" apparently curve fit every device function into a TABLE... differentiability be damned :-( ...Jim Thompson

What would that do? My preferred model would let the pin voltages force temperature, but not output any current.

But I made my own power computer in a couple of minutes, so I don't need to mess with (and then test) their model. I can still force the temps with a *dedicated* grounded power supply.

Looks like I have a mild thermal runaway in the real thing, so I need better heat sinking. I need to keep capacitance down, so I guess I'll have to buy aluminum nitride.

I've had excellent results doing extreme 100kV/us 10A switching with CREE's SiC MOSFETs. I seriously doubted their SPICE models would be worth anything in this kind of territory, so I took basic capacitance measurements and did a suite of analytical calculations. As stated, I had excellent results, this with an unheard-of 10MHz repetition rate. I had a struggle with failures in my driving ICs and transistors, and revisited that issue (4 times). But I never had any CREE SiC failures!

So I'd say don't waste your time with the SPICE stuff.

I Spiced'd it to see if my basic, pretty weird, topology would work, and I did one breadboard to sanity check the model. The Cree model looked pretty good compared to real life, except that their similated substrate diode had zero forward recovery time, and the real diode certainly has enough to matter.

Driving the Cree gate is tough; James can verify that claim. I'm using GaN fets for that, which turned out to be a whole nother adventure.

I can't measure the Cree temperature with a thermocouple; it's too hot to touch and the Omega meter says 3 degrees C. I guess the insane e-field freaks it out. Gotta go IR.