I'm playing games with logic devices trying to get them to do more than you might expect. A counter generates a pattern of bits that I want to gate t o make an enable. I don't want to add another part and I have a spare nega tive edge JK FF. It will do what I want if I connect the clk to the lsb of the counter and the next bit to the K and a couple bits up the chain is co nnected to the J input. The FF clocks out four pulses from the outputs in two seconds then a 2 second pause. Trouble is it takes 2 seconds to start.
I should get the pulses after one bit change (a quarter second) if instead of the clock and the JK inputs I use the set and clr inputs. The higher bi t can connect to the and the lower bit connects to the clear. For this to work the simultaneous set/clr outputs need to be known. Normally both outp uts go high which is good. Then when the fast clear goes off, the set is s till asserted and the Q_n goes low. The low pulse repeats four times just as I wanted it to until the set (the slow pulse) is removed and the reset c ontrols the outputs. The Qn is the output that toggles down.
The trouble is this isn't happening in LT spice and one of the parts data s heet seems to say something else.
TI and Nexperia use different behaviors with TI setting both outputs high ( confirmed on the logic diagram) and Nexperia giving the set presidence. On says they set both outputs LOW, but their logic diagram seems to indicate a forcing of highs... but the set and clr inputs are reversed. Likewise I think there are errors in the Nexperia logic diagram. It appears the reset being non-asserted disables the clock while I expect it is the other way a round.
What a mess. I guess I won't be able to use that particular feature. lol
I have no idea what the simulation model is doing. There is nearly no docu mentation on the LTspice DFLOP. It appears if the reset and set are assert ed simultaneously the reset wins controlling both outputs then when the res et is removed the set acts. But if the reset is reasserted while the set i s still asserted the reset is ignored. Once the set is removed and they ar e both applied the same thing happens, the reset rules, but once removed th e set continues to control the outputs.
WTF!???
I could try the SRFLOP. Are the real devices specified any better?