Simple? logic function using 74HC logic

for minimum propogation delay you need to do it like this.

A -----::::::::::::::::: or gate ::state machine::------. __ B -+---::::::::::::::::: `--| \ | ) 1 >-------- | .--|__/ `--------------------------' it looks like the state machine is an S-R flip-flop

with (A & B) feeding RESET and (B & !A) feeding SET

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Agreed.

Seems reasonable...

Unless I err, the second pulse is missing from X.

A----------------\__________________/-------\_______/---\___/---------

B-----------\________/---\_____/----------------\______________/------

R=A&B-------\_______________________/-------\__________________/------

S=B&!A_______________/---\_____/----\_______/---\_____________________

SR___________________/--------------\_______/------------------\______

X'=B|SR------\________/-----------------------------------------------

X------------\________/---\_____/-------------------------------------

The SET condition seems overly inclusive. But I have trouble pinpointing an appropriate condition. I think it can't be a purely combinatorial function of A and B.

Francois Grieu

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Unless I'm missing something, and you're talking something other than
combinatorial logic, your truth table seems to be missing an entry:
(View in Courier)

 A   B   X
---+---+---
 0   0   1 -----------B

For a 74F00:

http://focus.ti.com/lit/ds/symlink/sn74f00.pdf 

the worst case input-to-output delay is 7ns, so 3 gate delays from A to
X, or 2 from B tp X would easily met your 50ns spec. 

JF

I'm indeed talking something other than pure combinatorial logic. The state of the output X depends on previous history of the inputs, not only on the present state of the inputs.

My previous "words" statement was imprecise, and one case not illustrated in the diagram; things should have been:

- X is high and the system reset whenever A and B are both high;

- if A is high when B goes low, then X shall track B until system reset;

- otherwise, X shall remain high.

A--------\__________________/----\_______/---\___/-------\___________/----

B----\________/----\___/-------------\_______________/-------\___/--------

X-----\________/----\___/-------------------------------------------------

In precisely equivalent words, X is to be high if and only if - B is high OR - there has been no high to low transition of B with A high since the last time the condition (A and B) held.

The B to X delays must be low, in the order of 50 ns max @ 5V, for both transitions. There is only a single change of either A or B in any

200 ns time period.

Francois Grieu

B),

74HC74: 1-flip-flop set if B falls while A is high. 2-flip-flop cleared if both A and B high

1 This means that 3 things need to be anded and fed to the clock A, B/ and Q/. It can also be done with the D input fed with A or Q

2 This is a 2 input nand feeding the reset

Now just or Q/ with B to make the output

Francois Grieu schrieb:

Hello,

a simple solution using only gates and no delay or monostables is impossible. But may be there is a solution using gates and edge triggerd flipflops. If you use a falling edge triggerd flipflop and connect A to the clock input and B to the data input, the Q output remains high if A goes low before B. But you get a problem with the second fallig edge of A while B is low.

Bye

What happens when A goes low?

It needs internal states, and it either needs to be clocked damn fast or (as someone mentioned) it needs those internal states to feed gates that control X from B.

How many internal states do you need? Can you clock this thing from an asynchronous clock or does it have to be clocked by the edges of A and B?

--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com

B),

So, X =3D A * B + C (A or B anded with any function C...

Event B lowgoing while A sets flipflop, reset only when A*B asserts high and the C function is defined here as B while that flipflop is set

That, I don't get. X can only remain high if it were high to begin with... but maybe this just means C =3D high when flipflop is not set?

That alone never changes the output.

My previous "words" statement was a bit imprecise, and one case not illustrated in the diagram; things should have been:

- X is high and the system reset whenever A and B are both high;

- if A is high when B goes low, then X shall track B until system reset;

- otherwise, X shall remain high.

A--------\__________________/----\_______/---\___/-------\___________/----

B----\________/----\___/-------------\_______________/-------\___/--------

X-----\________/----\___/-------------------------------------------------

Yes.

Just one bit S: has there been a high-to-low transition on B with A set since the last time the condition A&B held. Then X = B | !S.

No, because the single clock at hand is not fast enough, and besides B has no defined phase relationship with that clock.

That's what I'm looking after.

Francois Grieu

So, X = (A .and. B) .or. C

(A .and. B .or.-ed with any function C...

Event B lowgoing while A sets flipflop, reset only when A .and. B asserts high; this will call for an edge-triggered flipflop, with reset.

74HC74? and the C function is defined here as B while that flipflop is set

(74HC74 trigger = .not. B, D input = A,reset input = A .and. B; outputs Q and .not. Q)

That, I don't get. X can only remain high if it were high to begin with... but maybe this just means C = high when flipflop is not set?

C = .not. Q .or. ( Q .and. B)

The startup state of the flipflop is undetermined, it's a good idea to use a master set or reset system signal to make it determinate. It's also a very good idea to put a Schmitt trigger (inverter or gate) on the input clock signal, to keep it from doing something ... odd.

"Francois Grieu" schrieb im Newsbeitrag news: snipped-for-privacy@gmail.com...

Hello Francois,

You should use an FF to build a small state machine.

A solution with a theoretical positive edge clock input D-FF with positiv reset:

CLK = B\ D = A OR Q CLR = Q AND A AND B

X = (Q AND B) OR Q\

WIth a real FF 74HC74 with positive edge clock-input and low reset:

CLK = B\ -> Inverter 74HC14 D = A OR Q --> 1/4 74HC32 CLR\ = (Q AND A AND B)\ --> 1/3 74HC10

X = (Q AND B) OR Q\ --> (1/3 74HC10 +Inverter) + 1/4 74HC32

You should use a 74HC14 for the inverters to get fast edges, especially if your A and B inputs have rise times slower than 100ns.

Best regards, Helmut

PS: You would save the OR-Gate at the D-input if you use a JK-FF.

You're right. I was thinking on this further, more state is needed so that the flipflop is only set when A goes from high to low while B is high.

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