When S and R are inactive, the flipflop reverts to normal clocked operation. If you're driving both of them high and low together, you've got a transition from a disallowed state (R and S both asserted) to the hold state (R and S both disasserted).
There's no guarantee as to what state it winds up in under those circumstances. If you go through an allowed state, i.e. bring R and S low sequentially, observing the setup and hold time specs, it'll do the right thing.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
On a 4013 D-FF, when you tie both the SET and RESET together to the same logic state, I see that it forces both Q and !Q to go high when a POS edge is triggered on these paired lines.
Looking at the Fairchild PDF, it does not say what happens to the outputs when both R and S are pulled low at the same time, but in reality it is forcing both outputs Q and !Q to go low, even though it's not in the truth table like that. I am investigating an existing circuit and there is a case where both these lines are synchronized in this manner and it's not intentional by any means that I can see, it would be a side effect in the design.
Personally, I see this as a race condition as to whom gets the trigger first, R or S in the POS edge? And for the 0 state, I don't see where it should make any difference on the outputs, but it does in this case.
Is this normal for all family of Data flips or just this one?
Jamie
The Fairchild PDF does show that pulling both the R and S up together generates a valid output for both Q and !Q to be logic
1, but for some strange reason, it does not document the behavior of both going down.. After debugging, I can tell you what it does ;), with a CD4013 bot Q and pull low, this is after they have both been high.We'll have to keep this in the back of our minds :)
Jamie
The disallowed state is disallowed because not all of its transitions are well defined, as you've discovered.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
The R and S inputs are static, not edge sensitive. If both are high, it forces both Q and \Q high.
It shouldn't do that. If you start with R and S both high, and then drop both simultaneously, one output will remain high and the other will go low... not sure which. Q and \Q should not be low simultaneously.
If you drop them not-sumultaneously, the last one wins.
That sort of behavior is pretty normal for flipflops. TTLs are usually active-low on set and reset, but the idea is the same.
-- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation
The old National data books showed logic diagrams for their flip-flops. The clocked ones all seemed to be some cascade of RS flipflops and gates.
When you pull both R and S active at the same time (which logic level is active depends on whether it's a two-NOR FF or a two-NAND ff) and the pull them both inactive simultaneously, you're basically flipping a coin as to what state the gate will fall into. Except that it's a coin with a long hang-time, it's loaded, and it comes from a bucket of coins that are all loaded, but differently.
At the edge of the transition the flip-flop is in a metastable state -- the two gates are each trying to force the other inactive, they're in the proverbial "ball bearing on top of a hill" state. Then an imbalance within the chip or random noise in the circuit starts to pull it in one direction or another, and finally it falls into one state or another.
"Doctor, it hurts when I do this!"
"Well, don't do that!"
-- Tim Wescott Wescott Design Services http://www.wescottdesign.com
Any "discrepancies" seen at the outputs depend on the internal connections - meaning characteristics seen of "same" device from one manufacturer will rather likely be different than from another manufacturer. If you do not like brand X, then try brand Y; else roll an "equivalent" using a PIC and software to get what YOU like.
This is pretty dangerous. You may get consistent behavior from one batch of chips, but a different batch, or a different vendor, would likely behave differently, ot totally randomly.
Jon
Yup. Here's the internals of a Motorola 4013 from some time in the
1970s.Best regards, Spehro Pefhany
-- "it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com
The R and S paths are asymmetric so the state, after both go low simultaneously, is probably repeatable. But I think it will depend on the clock level, because the master and slave asymmetries are opposite.
Too much work to figure out at 7 AM.
-- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation
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