clock generator

- J
- jason
  
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posted
18 years ago

Tue, Jul 5, 2005 12:15 AM

Hello All

Anyone can share the idea of designer a clock generator using cmos PLL technology? Do share with me any good link or material on this topic from basics to advanced level. Thank you

rgds and thanks Jason

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- J
- John Fields
  
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posted
18 years ago

Tue, Jul 5, 2005 2:28 AM

--
Google "4046" without the quotes and then, if you have any questions,
post back.

- B
- Boki
  
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posted
18 years ago

Tue, Jul 5, 2005 10:37 PM

Clock generator => VCO => PLL

inverse?

I don't understand...

Best regards, Boki.

"John Fields" ???????: snipped-for-privacy@4ax.com...

- J
- jason
  
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posted
18 years ago

Thu, Jul 7, 2005 5:57 AM

Hi All

It is a kind of clock generator that make use of PLL or DPLL(mixture ofanalog and digital circuit) . The aim is to investigate the jitter and also skew when load , temperature and power supply is varying, Anyone know of such a reference? Kindly help

thank you jason

- B
- Boki
  
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posted
18 years ago

Thu, Jul 7, 2005 2:25 PM

so you have to inverse it to see that? Still not understand..

Best regards, Boki.

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