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clock generator (PLL)

Hi,

I'm working on making a variable frequency clock generator using a PLL based on a TI TLC2933 VCO and an ADF4001 phase detector (instead of the TLC2933's on-board phase detector, as the ADF4001 has a SPI interface, and on-board dividers).

However, the ADF4001 is an RF part and I'm not sure if I'm using it correctly - just wondering if anyone can give me any hints if there is anything wrong with the following setup:

Both devices are on a 3.3V rail. I'm driving the REFin on the ADF4001 with a DC coupled, 4MHz, 3.3V CMOS oscillator - according to the ADF4001 datasheet, 4MHz is OK for a CMOS input if it's DC coupled.

The bit I'm a little unsure about is the RFinA and RFinB inputs. I've decoupled RFinB to ground via a 100pF capacitor and I'm AC coupling RFinA with a 0.1uF capacitor. Also, absolute maximum potential between RFinA and RFinB is +/- 320mV.

As the TLC2933 gives out a 3.3V square wave, I've put its output through a 62k+5.6k potential divider to bring the signal down to 270mV, before connecting to the coupling capacitor on the ADF4001 input.

If any of this sounds like it could cause problems, I'd be interested in hearing what you've got to say.

Thanks,

Steve

Reply to
Steve
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If you look at the diagram (Figure 3 in my copy of the datasheet), it looks like the RF input is a differential pair, biased to some voltage or other through 2k resistors. It should probably work ok with only a few tens of millivolts swing going into it but a couple of hundred millivolts sounds more reliable and less noisy. I think what you suggested doing sounds reasonable, though the internal 2k bias resistors will load down the waveform from your resistive divider smaller than you intended, since there is effectively 4k in parallel with your 5.6k. I would probably just delete the 5.6k resistor and you will get about the right voltage then. I would provide a PCB placement for a cap in parallel with the 62k resistor, in case a few pF here is needed to prevent any low-pass-filtering action due to stray capacitance or the chip input capacitance. I would also make sure that the 62k is physically reasonably close to the ADF4001, not at the other end of the line. I think that you probably ought to increase the

100pF cap, to match the other 0.1uF (100nF) cap that you used, because it has to be effective down at 4MHz.

Let me know how you get on, I shall soon be building something similar with a CMOS signal driving the ADF4001. I haven't used that chip yet but I have been planning the circuit, just as you are.

By the way, just out of interest what is your application?

Chris

Reply to
Chris Jones

Those resistor values you mention sound a bit high for use at RF.

The datasheet quotes input sensitivity in "dBm referred to 50 ohms" as -10 to 0 dBm. It doesn't state the input impedance, but figure 3 shows internal

2k bias resistors on the RF inputs - so your 5k6 resistor won't make much difference with this 2k in parallel.

This article shows a way to interface it to a 50 ohm system:

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They terminate the 50 ohm system with a 49.9 ohm load resistor, and capacitively couple into the ADF4001. 0 dBm across 50 ohms is about 320mV peak.

If you don't have a 50 ohm source, you don't need a 50 ohm termination.

Reply to
Andrew Holme

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