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cmos inverter

Hello All

Anyone know where can we find the delay time of a single cmos inverter(buffer) for technology ranging from 0.7um, 0.5um, 0.3um to

0.18um? Sort of like benchmarking? In fact, I only need to know about the delay time for 0.5um technology. Kindly let me know.

Also if there is a way to calculate, please share with me about it. If some parameters for each technology are needed, please let me know how to we get the parameters for each technology(from model files)?

If it is from model files, many of them are shown in symbols and the exact name of the symbol are not know, any site that introduce each of the parameters in details?

Kindly help Thank you

jason

Reply to
jason
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The way I qualify a CMOS process is by simulating a ring oscillator, any odd number of inverter stages, but the longer the better for accuracy. Then you can easily measure the delay thru one stage loaded by a similarly sized device.

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.
Reply to
Jim Thompson

Note that there are two types of CMOS inverters: single stage ones and triple stage ones. Their uses and behavior are wildly different.

--
Many thanks,

Don Lancaster
Synergetics   3860 West First Street  Box 809  Thatcher, AZ 85552
voice: (928)428-4073 email: don@tinaja.com

Please visit my GURU\'s LAIR web site at http://www.tinaja.com
Reply to
Don Lancaster

Thank you Jim and Don

Any good online material you can recommend for this ring osc simulation? I need a single stage cmos inverter. I will find out at the mean time too. Please share with me your opinion Thank you all

jason

Reply to
jason

Start with a minimum size device for the NMOS. See the process specs for this size.

Then size the PMOS width until the threshold is exactly at VDD/2.

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.
Reply to
Jim Thompson

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