Yeah I don't know if it's a model problem at this point or if this circuit is just a bust I'm curious now.
It would be amusing/sad if that referenced patent just didn't work at all. Maybe the crystal makes the "magic" happen
I think a ripple counter would work fine to divide down a clock from a faster Schmitt oscillator, also. Then I could use the fast clock for some other purpose. That'd be cool.
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It's not magic. Just that most people aren't familiar with the issues of d esigning an oscillator. I assume this is not a circuit which is important to operate in a real circuit. Oscillators like this can have intermittent startup problems. I just use oscillators these days. Easier. Even when t he oscillator is in an MCU they do a crappy job of specifying the crystal p arameters. You have to beg for things like ESR of the crystal. Pick the w rong part and it will work fine on the bench, them may not start reliably w ith changes in temperature, etc.
You could try working that thread again. I can't find the model you indica te at ADI (bought LT). Try copying the text in Harald's post and make helm ut's modification. Harald said that was what worked for him.
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I'm just gonna feed a faster Schmitt trigger-oscillator clock into a a long counter I think so I can divide it down to a few Hz and use the faster clock for some other purpose. The single gate or two-gate NAND schmitt oscillator is not sexy but it's pretty reliable.
You're right it might be possible to get this to work with fiddling in simulation but I need something that will work consistently IRL, not any point in spending much more effort on it.
I thought it would be cool if there were a way to make say a quad D flop self-oscillate and divide itself down but sounds like a challenge for another day
Packaged XOs are so cheap now it's barely worth making your own oscillator. Well, maybe a schmitt if the frequency accuracy doesn't matter much.
Small uPs usually have a pretty good internal oscillator.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
uP's are so cheap and easy that there's little reason for me to not recommend one for most simple projects right off the bat
This is a great tool, it lets you drag and drop little functional blocks like "voltage controlled" oscillators, logic gates, functional blocks of various types and bang it up to an 8 pin AVR in about 5 minutes:
But I don't turn down money because a client asks me to design something they'd like to build themselves without a uP and wants to pay me some cash for my nice-dinner-with-the-girlfriend fund for doing it
sim
of designing an oscillator. I assume this is not a circuit which is import ant to operate in a real circuit. Oscillators like this can have intermitt ent startup problems. I just use oscillators these days. Easier. Even wh en the oscillator is in an MCU they do a crappy job of specifying the cryst al parameters. You have to beg for things like ESR of the crystal. Pick t he wrong part and it will work fine on the bench, them may not start reliab ly with changes in temperature, etc.
dicate at ADI (bought LT). Try copying the text in Harald's post and make helmut's modification. Harald said that was what worked for him.
The circuit is the same as an inverter, just no Schmitt trigger.
The quad FF doesn't have the preset and clear controls that turn one stage into an inverter. You could wire one stage to be a divide by two, use a di fferentiator to produce glitches with a diode to clamp the low going pulses so they become positive pulses. That would be a tricky circuit.
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There's a niche for low-speed hairball logic-like circuitry, that being able to "program" a microprocessor visually and end up with a "circuit" but expressed in auto-generated code, but that is provably glitch-free and that runs on a general-purpose uP that this tool fills very nicely
ould
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e ePlaces like IBM, Bell Labs and EMI Central Research had teams of patent law yers, and a culture where the staff were encourage to put in patent queries .
One of my colleagues at EMI held the record for patent queries filed in any one year. None of them went through. One of the two I got resulted from wh at had struck me as a perfectly obvious point, but after I'd had to explain it to some half-dozen people I decided that it probably wasn't obvious to those skilled in the art. The patent examiners agreed.
-- Bill Sloman, Sydney
The innards of a master/slave D flipflop are huge; a simpler oscillator (ring oscillator) just takes an odd number of inverters, so in CMOS it starts at six transistors, maybe even two, no external capacitors/resistors required.
One generally uses other things, to minimize side-effects (power supply current spikes) , and timing components accurate over temperature, aging, device variation.
By grounding the clock, data input and PRE- input, the "huge" innards are all disabled other than a NAND gate and an output buffer. CLR- to Q- looks like a single inverter.
Crystals are good, oscillators are better.
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Rule of thumb: if a company decides to put a /new/ emphasis on getting patents, then someone has /started/ thinking of selling the company.
Yup; that was my experience too.
Yeah like the double-decker couch!
Zoinks! You've taken a wrong turn.
Let's split up, gang. If you're looking for an image, it's probably been deleted or may not have existed at all.
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This recently posted to the Previously-mentioned group:
"In the course of writing my 74LVC1G library I discovered that my first attempt at the '74 D flip-flop wasn't quite right: the truth table was correct except for when Set and Reset were both low. The datasheet states that Q and Qbar should both be high, but Q was in fact low.
I checked just the A device Dflop and found that the behaviour of Preset and Clear is complex and incompatible with *74 devices. Therefore, any 74xx series D flip-flop model that just relies internally on the A device Dflop will likely be incorrect. I checked Helmut's 74HC and 74HCT libraries and the '74 devices were incorrect.
I'm surprised that after all these years, nobody has spotted this subtle error with these libraries!
I haven't checked whether there are other device models in various libraries with asynchronous Set and Reset that also have this problem feature.
The truth table of the A device Dflop depends on the order that Preset and Clear are set. If Preset is set first and remains high and Clear is set later, Preset overrides Clear and Q remains high and Qbar remains low. If Clear is set first, then Q remains low and Qbar remains high. If both are set simultaneously, then Q and Qbar are latched in the states they were before before Preset and Clear were set.
If both Preset and Clear are set from t=0 (initialised), Q always remains low and Qbar remains high.
I have since found that
To correct the 74HC74 and 74HCT74 library model static truth tables requires that the A device Dflop Preset and Q are OR'd and Clear and Qbar are OR'd for the respective outputs, and the timing adjusted.
Regards, Tony Casey"
RL
Clearly this is not an easy issue to fully grasp. The last bit of this exp lanation is not correct I think. Rather than ORing the signals listed, the y should be NORed or low true ANDed (same thing, different ways of saying i t). From the earlier description of how the models currently work, I'm not sure this would properly account for the internal state of the FF however.
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going by fig 4
it should work as an inverter.
-- When I tried casting out nines I made a hash of it.
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