6-layer PCB stack up

What they sell as "standard" is what they can build out of the parts they have today. If you don't specify this stuff, you're in for a big surprise.

It's also the way to get crap. I guess it works for hobbyists.

The "return current" is coupled to the ground plane. If you slice and dice it, too, you will have problems.

Sorry but that is total crap. Its like saying a gas station puts gasoline in your car this week and next week its diesel. Utter nonsense. The company I'm referring to (Eurocircuits) has the stackups specified on their website and they make the boards themselves in several factories across Europe. They deliver what they promise.

Your assumptions maybe true for a shabby PCB broker who orders from this week's favorite Chinese. I wouldn't order PCBs from such a company to begin with.

I had wanted to make it 8 layers. But it must be within 0.047 to

What's EMC testing? This will go in a metal box in a laboratory. No need for testing. But that doesn't mean I don't care. It's just that I don't need to pass any sort of testing with my board in some plastic iPod case.

Thanks for the input.

Of course not. But you've got the dimensions wrong: the gap might be 0.25mm (i.e., 10 mil, or even less), not 1mm. This lets out a lot less flux already (both E and M).

Be interesting to see just how much crap gets lost over such a discontinuity; like a scope probe with ground clip, it's not going to be pretty by any stretch, but it's also not going to be as bad as DC intuition suggests.

This would only be true of a board with a single, slotted ground plane, which is silly by any measure. The correct analogy would be if you took that injured coax cable and wrapped it with copper foil tape, so that the shield is supported all around by a secondary ground plane. The current flows as displacement current in the outer jacket; high frequencies will hardly know the difference.

Very high frequencies will know the difference, on the order of slot width ~= 1/20th wavelength. Low frequencies will know as well, but that's easy, because at low frequencies you can simply hook a wire to either side of the gap and handle the LF current that way.

John uses many planes, and only two planes are required for operation -- a slot in one pour, or a gap between different pours, supported beneath by pours bridging said gap.

Tim

I rarely have a slot cut out of a plane. What I commonly have is a plane that has a bunch of power pours, pretty much paving the plane with patches separated by small gaps. That might be the "reference plane" to a surface microstrip, or we might have an embedded stripline between a solid ground plane and a multi-pour power plane.

If you treat the power plane like a solid sheet of copper, it works. The discontinuity that you typically get is comparable to the impedance variation you see from the fiberglass weave.

I don't know why people make such a big deal about reference planes and return currents and bypassing. On a multilayer board, most anything reasonable works. For fairly fast stuff, like FPGA clocks, impedance and crosstalk control does matter. I could teach someone most of what they need to know about this in 45 minutes.

is

Only if you specify exactly what it is you're buying. You just said you take what they give you. Make up your mind.

Wrong again. Even the top-tier companies will give you shit if that's what you order. You're obviously oblivious, or wrong about what your company is actually buying.

e.

t I

We had several houses that easily provide stock 5 mil and offered 2-3 mil prepreg so you could still do 8 layers, even 6 mil all the way would work.

EMC Testing, also called Compliance Testing, refers to ElectroMagnetic Compatibility Testing to meet the premise - thou shalt NOT disturb, and thou shalt not be disturbed by, other electronics.

For the US (FCC Part 15/18/22 depending) and Canadian (CSA) standards, and for Europe, CE approval process to allow import into Europe, EN?? standards.

However, in the US *if* you do not sell or rent, but provide as demonstration/evaluation unit; the unit is exempt. It is my understanding that *if* it is Test Instrumentation to be used in a lab (and is NOT marketed, nor expected by virtue of cost, complexity, etc to ever find its way outside the lab) the unit is also exempt. Therefore, you don't care, unless someone has a problem.

But, it would behoove a responsible manufacturer to meet a lot of 'implied' specs - things people expect a product to do, or in this case, not to do; in order to add credence to the quality of the unit.

It would be embarrassing if the unit while operating next to something in the lab suddenly started giving flakey measurements. A single incident could destroy a lot - confidence, reputation, etc.

Sometimes a metal box is not a cure-all for EMC. I've seen items miserably fail even inside a very solid metal box and nothing short of a major PCB relayout could fix it.

Again, if it's small run; trade time for $$. It makes the inevitable changes easier, too.

That's not as impressive to my boss as "getting this stuff right requires a lifetime of study of this big stack of (Howard Johnson, heh heh) books!"

Yes, this is a better analogy, and what I had in mind just a few moments ago whilst thinking about this at breakfast.

Interesting stuff. Thanks for the input.

So if you had this stack (not saying this would be done in a real PCB):

1. signal trace
2. power layer with multiple tiles of power, all separated by gaps
3. solid ground plane

that the impedance of traces in layer one would be computable based on the distance to layer 2, and that the gaps wouldn't matter because layer

What about a situation like this, typical of the 4-layer boards I get from Advanced Circuits, if I don't ask for anything non-standard:

layer 1

In this case the inner layers are quite far apart. So for whatever inner layer is GND, the signal on the far side will be 0.010in from the power plane with cuts, and 0.050in from the continuous ground plane.

Does this start to become a problem?

Hopefully some day I'll have time to make some experiment boards (fat chance).

Yes. The gaps are, or should be, small, like 8 mils maybe. Cruising over a gap, a signal can barely see it. Its electric field won't penetrate much into the gap, and the capacitances of the layer 2 pours to layer 3 are much higher than the c from the trace to the layer 2 patches. Plus, there will be bypass caps.

We most often use layer 2 for ground, to keep the L1 traces quiet and to have minimum via inductance to ground. But that probably doesn't matter much, either. A lot of this stuff is like eating garlic to keep vampires away... it works!

Looks OK to me. L2 could be ground and L3 could be the power plane, with an occasional trace snuck in if needed. A 50 ohm trace on the top or bottom would be about 18 mils wide, perfectly reasonable.

When I do a production board, I try to add test traces with SMAs, and sometimes add an SMA to hit a power plane voltage. I can TDR the test trace to see how well my impedances hit their tagets, and I can TDR the power plane on the bare board, or check plane noise on a running board.

Here's one. The test trace is just above the logo. It passes through four signal layers. I'll post a TDR later maybe.

I should have done more traces, just for fun, specifically some that cross power pour patches. Oh well, next chance.

Don't think of a plane as being a shield to end all shields. It isn't. Depending on what you're doing, be careful. The return current appearing in your 'solid' plane will 'punch through' from the solid plane layer and also appear in your next layer. The layer you thought was shielded by a solid plane. That is, *IF* you're doing extremely low noise design. You'll start seeing the current patterns cause voltage 'lift' along your next layer. And a cut/gap worsens that, too. Course, this was for a 100MHz 22 bit DAC system. Doesn't take much to affect.

One thing that bugs me about your post is that you spend a lot of time talking about "capacitance." Nobody cares about capacitance. The only important quantities are the reactances, and those vary with frequency.

As a result, your advice is probably more valid at higher frequencies than it is at lower frequencies, and the low end still matters to a lot of people. An example being interplane capacitance as a bypassing mechanism... fine at 500 MHz, maybe. But the PCB dielectric will not hold enough energy to serve as a useful bypass at HF, even for low current circuits. And if the planes aren't truly equipotential with AC ground, then they are going to pick up and re-radiate energy. Maybe that's a problem, maybe it's not.

Terms like "not much" don't help when your interplane C turns out to be more effective at coupling than at bypassing. And if slot antennas don't terrify you, you're either really good at your job, really bad at it, or working on something uninteresting.

As long as the experiment's underlying model is accurate. What works well on your board may get me (or Mr.CRC) into a world of hurt.

-- john

When a person speaks of "capacitance" at high frequencies, what is really meant is "the impedance of the structure is less (usually significantly less) than the impedance of the related signal lines".

A trace's characteristic impedance might be 50 or 110 ohms or whatever on L1, relative to the ground plane on L2, but the impedance from any geometry in L2 (disparate pours, or a slot in a single pour, etc.) relative to the (solid or overlapping) ground plane on L3 beneath it results in a vanishingly small impedance (< 10 ohms) between those pours/planes for "most" higher frequencies.

For lower frequencies (where the induced wave has had a chance to bounce around the bounds of the pour a few times), the inductance of vias, traces and packages comes into play and bypass caps take over. As a result, the impedance of the pour may vary quite a bit with frequency, and you may get unlucky with particular combinations of pour shapes, and where the bypass caps are placed on them (i.e., avoid harmonically related spacings to prevent bypasses enhancing nodes at some resonant frequency), but for the most part, with random placement, you'll have good luck that any resonances that occur will still be low impdance.

Note that a trace crossing a slot in a single pour is identical to it crossing separate pours, as long as the frequency is higher than the quarter wave length to the nearest corner of the slot -- until the energy reaches the end of the slot, it doesn't "know" that it actually IS a slot, or just another gap.

A slot antenna, roughly speaking, looks like an inductance (defined by the flux that goes through the enclosed slot area) parallel with a capacitance (the capacitance of the sides of the slot to each other, roughly), limited by the Q of copper and radiation resistance. If L is small and C is large (which are both true when a slot is underlaid by a contiguous ground plane), then even for very high Q (which is unlikely, because the inductive Q will be poor with so much shielding), the impedance of the resonant tank thus formed can still be very small. Though the resonance will be detectable, it need not be significant in relation to digital signals (e.g.,

signal

planes.

Um. Vias to other layers adjacent to or inside the pad is not impermissible. It depends a lot on how many pads need controlled impedances and why.

?-/

One usually wants to minimize vias, namely make as many connections as possible on layer 1. So you do what works, which wrecks direction discipline.