a good six layer PCB stack-up recommendation but...

and what's the exact thickness between L3 and L4?

I calculated as follows: solder mask Er =3D 3.3 / 0.7 mil FR4 Er=3D4.2.

z L3 =3D 50+ z L4 =3D 50+ not bad for 60 ohm trace...

The edit job turning a copy of figure 7 into figure 8 was botched.

Ask your fabricator for the tolerance you will get if you specify the suggested 30 mils, or whatever you actually specify.

So you calculate the same impedance for the 5 mil and the 6.5 mil dielectric? While there is no reason you can't use different trace widths on these layers to actually get the same impedances (within manufacturing tolerance), there is no reason to make this layout asymetrical either.

You should take these app note stackups as suggested ideas to consider during your design, not as actual usable designs.

For really good info on how the details of your board design affect your signal integrity, subscribe to the signal integrity mail list, search the archives for book recommendations, and read a few.

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