4017 chip won't behave!

It uses a chain of seven CD4017BE decade counters. The first in the chain gets clock pulses from a 555 running at about 10Hz. I take the last output from this chip (puts out one pulse for every 10 input pulses) and feed it to the input of the next chip where the same thing is done and so on so the pulses get time-divided by 10 at each stage. All's fine up to decade 4, then something odd happens. Instead of just pulsing, the output goes high and remains high until the next pulse comes along and toggles it back to low, so this stage's output is high for far too long.

believe I've paid proper attention to grounding and decoupling. Funny thing is, if I transfer the components over to proto-board, the problem disappears. Do these symptoms ring a bell with anyone? Is the 4017 particularly layout-sensitive?

Missing power or ground connection?

Most chips in the CD series will still work without at least one of these connections by powering or grounding themselves from the input-catching diodes as long as at least one input is in a suitable state. When all inputs go to '0' (if the + is missing) or to '1' (if the Ov is missing) the chip will get in a tangle. The chip will also be isolated from its power supply decoupling, so it will be susciptible to spurious effects from sharp edges on input waveforms or even nearby tracks.

A floating reset line can also cause havoc.

--
~ Adrian Tuddenham ~ 
(Remove the ".invalid"s and add ".co.uk" to reply) 
www.poppyrecords.co.uk

Could be signal bounce in your "rat's nest"?

More likely with 74LS and anything else with enough speed and drive (74HC, AC, etc.), and rather unlikely with the weak outputs from CD4k, but...

This is different from supply decoupling: a sufficiently long wire or trace will bounce (potentially causing multiple transitions) or rise slowly (confusing clock inputs). The result can be seen on the 'scope.

If nothing else, you can try RC-filtering the signals and adding a schmitt trigger buffer to maintain the necessary edge speed for the clock input.

Tim

-- Deep Friar: a very philosophical monk. Website:

I've been having problems with a timer circuit I'm building. It uses a chain of seven CD4017BE decade counters. The first in the chain gets clock pulses from a 555 running at about 10Hz. I take the last output from this chip (puts out one pulse for every 10 input pulses) and feed it to the input of the next chip where the same thing is done and so on so the pulses get time-divided by 10 at each stage. All's fine up to decade 4, then something odd happens. Instead of just pulsing, the output goes high and remains high until the next pulse comes along and toggles it back to low, so this stage's output is high for far too long. For this prototype I'm using rat's nest on PCB construction and believe I've paid proper attention to grounding and decoupling. Funny thing is, if I transfer the components over to proto-board, the problem disappears. Do these symptoms ring a bell with anyone? Is the 4017 particularly layout-sensitive? It's driving me nuts.

Any ideas?

, t

The 4017 already has Schmidt trigger input anyway. I did consider long trac es, but they're not long. Plus when I hook the thing up using proto-board I 'm using patch wires that are several inches long and they don't seem to ca use any problem; the thing seems to prefer protoboard and long patch wires to my PCB arrangement!

ain of seven CD4017BE decade counters. The first in the chain gets clock pu lses from a 555 running at about 10Hz. I take the last output from this chi p (puts out one pulse for every 10 input pulses) and feed it to the input o f the next chip where the same thing is done and so on so the pulses get ti me-divided by 10 at each stage. All's fine up to decade 4, then something o dd happens. Instead of just pulsing, the output goes high and remains high until the next pulse comes along and toggles it back to low, so this stage' s output is high for far too long.

've paid proper attention to grounding and decoupling. Funny thing is, if I transfer the components over to proto-board, the problem disappears. Do th ese symptoms ring a bell with anyone? Is the 4017 particularly layout-sensi tive?

The main idea is to read the datasheet with comprehension. Phrases like "ea ch decoded output remains high for one full clock cycle" and " a carry out signal completes one full cycle every 10 input clock cycles" should be clue s. The datasheet is telling you the first O9 output stays high for 0.1 sec, the period of the 555 clock, and has a period of 10x0.1=1 sec. So the se cond counter O9 will remain high for 1s and has a period of 10 sec. The thi rd counter O9 remains high for 10s and has a period of 100 sec, and the fou rth counter O9 remains high for 100s and has a period of 1000 sec.In your c ase, the simplest fix to get the final output pulse width you want is to us e another 555 like so: Please view in a fixed-width font such as Courier.

. . . . . V+ . | . .---[R]------+ 0.7xRC . | | 555 . | -------------- ->| | | | . | | | __| |__ . O9 +-----+TRIG DIS|-. . _. ..._ | | | | . | | >--|-----|RST GND | | . __| |__ | --------------- | . | | | . +-------------|--------' . C | | . === | . | | . '-------------+ . | . --- . /// . . .

ain of seven CD4017BE decade counters. The first in the chain gets clock pu lses from a 555 running at about 10Hz. I take the last output from this chi p (puts out one pulse for every 10 input pulses) and feed it to the input o f the next chip where the same thing is done and so on so the pulses get ti me-divided by 10 at each stage. All's fine up to decade 4, then something o dd happens. Instead of just pulsing, the output goes high and remains high until the next pulse comes along and toggles it back to low, so this stage' s output is high for far too long.

've paid proper attention to grounding and decoupling. Funny thing is, if I transfer the components over to proto-board, the problem disappears. Do th ese symptoms ring a bell with anyone? Is the 4017 particularly layout-sensi tive?

Revise the 555 one-shot to be as shown:

Please view in a fixed-width font such as Courier.

. . . . . V+ . | . .-[R]------+ 1.1xRC . | | 555 . | -------------- ->| | | | . | | | __| |__ . O9 .--[10K]-+----|---+TRIG DIS|-. . _. ..._ | | | | | | . | | >-+-------------|---|RST GND | | . __| |__ | | --------------- | . | | | | . | +-----------|--------' . 470p| C | | . === === | . | | | . '----+-----------+ . | . --- . /// . . .

schreef in bericht news: snipped-for-privacy@googlegroups.com... HI all,

I've been having problems with a timer circuit I'm building. It uses a chain of seven CD4017BE decade counters. The first in the chain gets clock pulses from a 555 running at about 10Hz. I take the last output from this chip (puts out one pulse for every 10 input pulses) and feed it to the input of the next chip where the same thing is done and so on so the pulses get time-divided by 10 at each stage. All's fine up to decade 4, then something odd happens. Instead of just pulsing, the output goes high and remains high until the next pulse comes along and toggles it back to low, so this stage's output is high for far too long. For this prototype I'm using rat's nest on PCB construction and believe I've paid proper attention to grounding and decoupling. Funny thing is, if I transfer the components over to proto-board, the problem disappears. Do these symptoms ring a bell with anyone? Is the 4017 particularly layout-sensitive? It's driving me nuts.

Any ideas?

Reading the thread so far there must be something wrong on your PCB. A short, an open, a wrong or missing connection, a bad solder joint or something like that. I simply can't come to another conclusion. Finding it may take some old-fashioned, tedious legwork. Use your eyes, maybe a magnifier and an ohmmeter that can measure real low resistances. Power- and ground connections are primary suspects, as stated already but there are no non-suspects. Did you try to increase the clock and check the circuit's behavior with a 'scope? As the breadboard version works, one does not expect flaws in the schematic. Nevertheless, if you can show it somehow I'd like to look at it.

petrus bitbyter

Perhaps I can load something up to abse if it's still possible. Thanks for your comments and I fully agree with what you say, but Fred Bloggs has just raised other valid points which need to be looked at (thanks, Fred) but th ere is still no explanation for why it works one way on breadboard and anot her way on PCB!

paid proper attention to grounding and decoupling. Funny thing is, if I transfer the components over to proto-board, the problem disappears.

Check to be sure you've connected all the unused inputs; the extra capacitance of a protoboard can mask floating-input issues.

r your comments and I fully agree with what you say, but Fred Bloggs has ju st raised other valid points which need to be looked at (thanks, Fred) but there is still no explanation for why it works one way on breadboard and an other way on PCB!

One explanation is that you misidentified a timing capacitor or resistor fo r the 555 astable on the proto-board and it is oscillating at a much higher frequency there.

On Monday, 10 December 2012 22:59:43 UTC+1, snipped-for-privacy@gmail.com wrote :

:

for your comments and I fully agree with what you say, but Fred Bloggs has just raised other valid points which need to be looked at (thanks, Fred) bu t there is still no explanation for why it works one way on breadboard and another way on PCB!

for the 555 astable on the proto-board and it is oscillating at a much high er frequency there.

It's *only* the problem stage that I have rebuilt on protoboard; it's still being fed by the output from the last good stage of the rat's nest.

ters.

I've paid proper attention to grounding and decoupling. Funny thing is, if I transfer the components over to proto-board, the problem disappears.

tance of

You mean unused OUTputs, surely? There's only one clock input line. But if you DO mean unused outputs (pins 1 through to 7) they're not connected to a nything; I just cut their leads off to save having to drill extra holes tha t wouldn't be used anyway. I'm guessing it's safe to leave unused outputs f loating, right? They don't have to be grounded or whatever do they?

All CMOS INPUTS must be tied high or low - they do not like to float. Outputs don't have to be connected to anything. Have you thought of getting a copy of the CMOS cookbook by Lancaster? Full of good information on the 4000 series.

e:

unters.

ve I've paid proper attention to grounding and decoupling. Funny thing is, if I transfer the components over to proto-board, the problem disappears.

citance of

f you DO mean unused outputs (pins 1 through to 7) they're not connected to anything; I just cut their leads off to save having to drill extra holes t hat wouldn't be used anyway. I'm guessing it's safe to leave unused outputs floating, right? They don't have to be grounded or whatever do they?

You need to make more quantitative observations. Telling us the final outpu t pulse is "far too long" doesn't cut it. At your clock frequency the final stage outputs are supposed to be high for 100 seconds, and they're suppose d to last high until the next clock pulse comes along. How long are they hi gh now and how long do you want them to stay high? It may have been the rat s nest was in error, it's really easy to get unwanted cross-coupling into i nputs with messy wiring, so the last stage in the rats nest could be gettin g double triggered on its clock input.

l

Oh, I wasn't aware of that. I've just basically 'plugged' the output of one 4017 into the input of the next with no pull-down resistors at all; never occurred to me that might be necessary, quite honestly. I'll modify accordi ngly. Hopefully that might fix that aspect of the problem. Many thanks!

put pulse is "far too long" doesn't cut it. At your clock frequency the fin al stage outputs are supposed to be high for 100 seconds, and they're suppo sed to last high until the next clock pulse comes along. How long are they high now and how long do you want them to stay high? It may have been the r ats nest was in error, it's really easy to get unwanted cross-coupling into inputs with messy wiring, so the last stage in the rats nest could be gett ing double triggered on its clock input.

I see. Well obviously I've made a fundamental mis-assumption about how thes e chips work. I'd assumed the pulse duration (the ON state)would remain the same throughout the chain of 4017s and that only the OFF time *between* th em would increase. Clearly from what you say that's not what happens. So ba sically if I want to end up with say one, one second long 'high' on the fin al output after a delay of 7 days (for example) I need to back calculate so the first pulses from the 555 have a much shorter ON duration than 1 secon d. That's what your suggested mod is designed to do, I guess? I can see tha t now. Many thanks for the clarification.

On Tuesday, December 11, 2012 10:25:35 AM UTC+2, snipped-for-privacy@virgin.net wrote :

ne 4017 into the input of the next with no pull-down resistors at all; neve r occurred to me that might be necessary, quite honestly. I'll modify accor dingly. Hopefully that might fix that aspect of the problem. Only the unused inputs need pullups or pulldowns. If they are connected to a permanently enabled output then they don't need them.

4017 into the input of the next with no pull-down resistors at all; never occurred to me that might be necessary, quite honestly. I'll modify accordingly. Hopefully that might fix that aspect of the problem.

--
CMOS inputs only require being pulled high or low if they aren't 
connected to anything.  That is, if an output is connected to an 
input, then a pull-up or a pull-down resistor is neither necessary or 
desired. 

Unused inputs need to be connected directly to Vcc or GND, with no 
resistor.

All the 'reset' pins in the chain of 4017s I have tied to ground via 10k resistors. Looks like another thing worth investigating....

pulse is "far too long" doesn't cut it. At your clock frequency the final stage outputs are supposed to be high for 100 seconds, and they're supposed to last high until the next clock pulse comes along. How long are they high now and how long do you want them to stay high? It may have been the rats nest was in error, it's really easy to get unwanted cross-coupling into inputs with messy wiring, so the last stage in the rats nest could be getting double triggered on its clock input.

chips work. I'd assumed the pulse duration (the ON state)would remain the same throughout the chain of 4017s and that only the OFF time *between* them would increase. Clearly from what you say that's not what happens. So basically if I want to end up with say one, one second long 'high' on the final output after a delay of 7 days (for example) I need to back calculate so the first pulses from the 555 have a much shorter ON duration than 1 second. That's what your suggested mod is designed to do, I guess? I can see that now. Many thanks for the clarification.

Take a look at the timing diagram on page 4 of the 4017 data sheet at:

and you'll see that the outputs advance with each leading edge of the clock.

That means that if you ripple clocked the chain, the leading edges of the output used to drive the next higher stage would be ten times wider than the edges of the clock being used to drive the lesser stage, the result being that the output pulse widths would increase by a factor of 10 for each counter in the chain.

If you want your final output pulse to be as wide as one period of your 555's output, then the way to do it is shown in Figure 12 on page

15 of the data sheet.

There may be better counters out there for your application, depending on what it is. Can you share and post a schematic of your circuit somewhere?

--
JF