4017 chip won't behave!

I'd like to stick to something close to the original concept. The circuit John Fields posted, if it can be fixed-up, would be close to ideal for me.

--
Then you obviously can't see the fact that a device with a million 
transistors in it is more likely to fail than one with a hundred in 
it.
Reply to
John Fields
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lution.

t's why I'd like to stick to something close to the original concept. The c ircuit John Fields posted, if it can be fixed-up, would be close to ideal f or me.

that's not the point, everything can fail if you build something with transistors and it fails it is the transistors fault. if you build it with an uP irt's the uPs fault

And is more likely to fail? a single tested part with 1mill transistors or 10 * 100 transistor ics, 100's of solderings and what not

it all depends

-Lasse

Reply to
langwadt

I'd like to stick to something close to the original concept. The circuit John Fields posted, if it can be fixed-up, would be close to ideal for me.

Excess complexity equals asking for trouble. ...Jim Thompson

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| James E.Thompson, CTO                            |    mens     | 
| Analog Innovations, Inc.                         |     et      | 
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Reply to
Jim Thompson

ution.

's why I'd like to stick to something close to the original concept. The ci rcuit John Fields posted, if it can be fixed-up, would be close to ideal fo r me.

please enlighten me, in what way does instruction execution time have any relevance?

you can pick 1MHz if you like and it'll be microseconds

just be sure to get a really really really good clock reference if you want that seven day period to be accurate down to microseconds

-Lasse

Reply to
langwadt

solution.

why I'd like to stick to something close to the original concept. The circuit John Fields posted, if it can be fixed-up, would be close to ideal for me.

--
OK, let's say you have a subroutine which generates 1ms ticks and you 
want to use it to generate a 100ms delay. 

Looking at Motorola's 68HCXXX code for a jump to a subroutine can 
result in 7 machine cycles to execute the instruction, and the return 
from the subroutine costs 6 machine cycles. 

That's 700 cycles for the JSR and 600 for the RTS, a total of 1300. 

Now, if you're running the thing with a 1µs clock and a machine cycle 
is 2 clocks, then your 100ms is going to be - instead of 100ms - 
101.26ms. 

Plus, you'll need an index in to keep track of how many 1ms ticks have 
gone by, so that's even more error added, all because you thought 
instruction execution time is irrelevant.   


> 
> 
>> --- 
>> 
>> >you are concerned about the few nanonseconds it takes to set an output 
>> >when 
>> >the 7 days has passed? 
>> 
>> --- 
>> So this thing is running about a 300MHz clock? 
> 
>you can pick 1MHz if you like and it'll be microseconds
Reply to
John Fields

:

solution.

hat's why I'd like to stick to something close to the original concept. The circuit John Fields posted, if it can be fixed-up, would be close to ideal for me.

why on earth would you use a subroutine to generate a delay?

setup the timer to do X ms ticks and count, done ..

t

you seem to be doing it already ;)

so use a timer and instruction time has no relavance

-Lasse

Reply to
langwadt

lution.

t's why I'd like to stick to something close to the original concept. The c ircuit John Fields posted, if it can be fixed-up, would be close to ideal f or me.

so when you make an IC has self-calibration procedure built-in and uses more transistors than a discrete solution that does more or less the same it is asking for trouble?

-Lasse

Reply to
langwadt

solution.

That's why I'd like to stick to something close to the original concept. The circuit John Fields posted, if it can be fixed-up, would be close to ideal for me.

--
Lots of reasons, but I see you haven't gotten there yet.
Reply to
John Fields

:

ote:

ed solution.

. That's why I'd like to stick to something close to the original concept. The circuit John Fields posted, if it can be fixed-up, would be close to id eal for me.

the

no, set the timer to auto reload and it'll keep ticking at X ms

the few instruction it takes to see that it has ticked and increment a count does not accumulate

tput

you seem to be working real hard to make up artifical reasons why solving a problem with a uP solution in a single 50cent 8 pin IC is an inferior solution to a bunch of logic ICs

u

and that is precisely what you would do in a uP

-Lasse

Reply to
langwadt

You could get away with 3x 74HC40103 downcounters and lose the output decode and one-shot, but the drawback is you have to tie 24 preset bit inputs to 1s and 0s. So it's not as easy to put together as the 4017 approach.

Reply to
bloggs.fredbloggs.fred

solution.

why I'd like to stick to something close to the original concept. The circuit John Fields posted, if it can be fixed-up, would be close to ideal for me.

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Dunno what their game is,

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Reply to
Jasen Betts

that would be doing it the hard way.

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Reply to
Jasen Betts

and one-shot, but the drawback is you have to tie 24 preset bit inputs to 1s and

0s. So it's not as easy to put together as the 4017 approach.
--
I've posted a simpler solution on abse using a 4020 and a 4024. 

Check out Re: Simpler 7 day counter.
Reply to
John Fields

this Lasse character's inability to see reason. I stated I wasn't bothered if the timer was half a day out by 7 days, yet he's going on about microsecond precision which is *totally not necessary* for my purposes. I guess he didn't read the very simple spec I outlined. If I went down the route he suggests I'd

*never* get the damn thing running. NEVER!
--
I tried emailing you at the virgin.net address, but it bounced. Do you 
have another address? 

BTW, I've come up with a simple 5 chip solution for the timer 
including the clock, the decode and control circuitry, and the output 
pulser.
Reply to
John Fields

solution.

why I'd like to stick to something close to the original concept. The circuit John Fields posted, if it can be fixed-up, would be close to ideal for me.

Is it? That entirely depends on the devices I think, and what failure mode your are talking about. Most of the recent microcontrollers I have seen seem to have 2kV ESD pin ratings. I wonder what the equivalent rating is for 4000 series CMOS?

What is the relative reliability of a modern single chip microcontroller vs a board full of CMOS logic?

--

John Devereux
Reply to
John Devereux

Brainless much?

That's what he said. A single failure mode is far more likely on the million transistor element device.

Works. Doesn't work. Real simple.

Whoopie!

Do you know how ANY modern chips are fabbed?

Relatively miles from your flawed assessment.

Reply to
ChairmanOfTheBored

over this Lasse character's inability to see reason. I stated I wasn't bot hered if the timer was half a day out by 7 days, yet he's going on about mi crosecond precision which is *totally not necessary* for my purposes. I gue ss he didn't read the very simple spec I outlined. If I went down the route he suggests I'd *never* get the damn thing running. NEVER!

Yup. I'll be mailing you shortly. ISP problems this end causing me grief! : (

Reply to
orion.osiris

Ask them, not me. I don't see the United States on that list. It looks like poorly composed boiler plate that you are supposed to delete the areas you do sell to.

It was listed in US dollars, on the US site. If the really don't ship to the US, then file a compliant with Ebay. I had no problem buying several. They are the reason i was asking about a crimper for Berg/Dupont header terminals a while back.

Reply to
Michael A. Terrell

--
Done!
Reply to
John Fields

It's not getting there for some reason.

Reply to
bloggs.fredbloggs.fred

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