# How to design this circuit?

• posted

Might be helpful to describe what you're trying to accomplish. What you're asking is probably impossible in the general case. But there may well be techiniques to solve your overall problem.

Wasn't there a song about that? mike

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• posted

[100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax

You make a Phase Lock Loop by running a voltage controlled oscillator (VCO) at 100 times the frequencies, that is variable between 72Khz and 2.16Mhz. This forms the output. You take this output and divide it by 100 in two decade counters. The output of the second decade (div by 100) is compared to the input frequency with a Phase Detector. The output of the Phase Detector is an analog voltage. That voltage appropriately amplified and filtered drives the VCO locking its frequency onto the input frequency. In this scheme, the output will track the input times 100. Some care will have to be exercised to insure that the Phase Lock Loop and VCO have sufficient bandwidth to track at the maximum rate required. There are standard chips available to assemble this device. BTW it's a special case of a frequency synthesizer. Bob

• posted

How fast a lock (in terms of input cycles) before the output reflects

100x input?

How fast/often does the input frequency change?

If the answer to the first is >3 cycles, and the answer to the second is not too often, then you could probably do it with a microcontroller.

720hz to 22khz is not very fast. Microcontroller could measure a cycle or two of input, and start producing 100x output pulses. Some have hardware that would help, but with speeds that slow, if the tolerance is fairly low, should be no problem with modern microcontroller speeds even entirely in software.

sdb

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• posted

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It can't be done exactly if you don't know when the next transition
will occur.```
• posted

I'm looking for some way to figure out a circuit that will lock onto a signal (0-5v, binary) in such a way that no matter what the current frequency of the input signal (ok, within reason, 720 p/s to 21600 p/s), the output signal would be 100 times the input frequency.

In other words, I'd like to have 50 equally spaced pulses occur between consecutive transitions of the input signal?

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• posted

It sounds like you want a frequency multiplying Phase Lock Loop. Look at the app. notes on the CD4046.

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• posted

Hi John,

Unless you wait until the next transistion, place the 50 pulses in between and then pipe the whole chebang back out. Would be a nice app for a microcontroller. Kind of like how they used to do content monitoring on radio and TV where a tape ran through meanders and they could stop it in time if someone let off a rant.

Regards, Joerg

• posted

I can think of two promising ways to make this work. In general, since the circuit involves predicting the future, it is impossible to make it work perfectly.

But, if you know that the pulse repetition rate doesn't change too much from pulse to pulse, then it might work satisfactorily in practice. Or if you can tolerate a delay.

Option 1: You can use a digital approach with a CPLD or microcontroller. The idea would be that you use the last period as an estimate for the current period, and spit out your output pulses accordingly. In a microcontroller, you might have to use a PWM or some kind of special output. In a PLD, you can have a custom counter running much faster than your maximum input frequency.

If a delay of one pulse is tolerable, you might be able to make it work really well because then you would know the exact period ahead of time.

Option 2: Use a phase lock loop (PLL) where the VCO output is divided down by 100 prior to being fed into the reference input. It might be a challenge to make a PLL stay locked over this frequency range. I don't know that much about PLL's. You might have to do it all at a higher frequency, then mix down prior to the final output.

If you go with option 1, a DDS or NCO could possibly be used. It might be pretty easy to build the NCO into a CPLD.

If I had to prototype this quickly, I would probably try to put the whole thing into a CPLD.

HTH!

--Mac

• posted

And the problem with a CMOS 4046 PLL would be....?

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Many thanks,

Don Lancaster```
• posted

Only use a National (Fairchild now?) 74HC4046 or maybe a Motorola (ON now?) 74HC4046. The former RCA version (whatever brand they are called now, I can't keep up with it) 74HC4046A has a VCO that only works over a narrow frequency range. The National and Motorola ones are not directly interchangeable as they call for different oscillator component values but they will reach 5 MHz.

• posted

Kinda OT, but if you've got OpenOffice installed, I'm working on an alpha version of a 4046 spreadsheet VCO calculator. (Disregard the scribbles, it's a work-in-progress...) If you can't see the image, you enter Vdd, R1, R2, and C1 and it calculates Max,Center, and Minimum VCO frequency. A separate section takes Vdd, fMax, fMin, and C1 and gives R1, R2, and maxium Id.

• posted

You recall correctly. It's only good for 400kHz at 5V.

To the OP- you need the PLL and a divide-by-100 counter. The divided signal is locked to the input signal, so the VCO output will be 100 * then input frequency.

Best regards, Spehro Pefhany

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• posted

[...]
21600 * 100 = 2160000 IIRC you can't do 2MHz with a CD4046 at 5V

Use a HC4046.

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• posted

In article , Mark Jones wrote: [...]

I my Yahoo groups access seems to be on vacation today.

Based on your discription I'm assuming you didn't include the following.

You should also include the effects of hooking R1 and R2 to slightly positive voltages. (Yes, I have done this for a good reason)

The stray capacitance on the capacitors leads lowers the frequency slightly. A method to insert this may be nice.

Also, did you know that different makers 4046 work slightly different near the ends of the control range? This makes non-sense of any general program when the ends of the travel are involved. You should warn of this.

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• posted

I know from experience that some HC4046s will go to 20MHz when the Vc pin is at Vcc. They do so with a very non-linear jump near the top of the span.

None of the 4046 product lines really interchange well. It is best to either specify one maker or make your circuit sloppy enough to handle the difference between 2 makers.

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• posted

As others have said, it cannot be done in real time because there is no way to know when the next pulse is going to happen. However... If one sampled the input at a high rate, and stores the samples for a long period of time (say 2 mSec), then logic could "look" at pulse N and pulse N+1 and determine the time between them, and then create 100 pulses between them (as they travel down the equivalent of a digital delay line) with a resolution of the sampling rate. Then these pulses can be fed to the output at the proper times; they will be delayed (at minimum) by the time between the Nth pulse and the (N+1)th pulse. That means the longest delay will be at the longest time between any two given pulses, and that the delay will vary as the input pulse timing varies.

• posted

That's a good idea. I've been designing it based around the formulas found in a CMOS 4046 datasheet, which exact model I forget at the moment. Any chance you'd know how R1&R2 voltage affects frequency (mathmatically?)

Good point. :)

So it seems! How counter-intuitive. :)

Thanks.

• posted

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The problem wouldn't be with the 4046, necessarily, it would be with
the concept of trying to stuff a given number of equally spaced pulses```
• posted

I'm following up to my post to give more information. Basically, I wish to "enhance" the resolution of a rotary encoder. I could do this in the following way:

Take a high frequency signal, say 16MHz, and count the pulses for each high/low part of the signal. Use the last 3 to get an idea (average and direction) of where the signal is going, and use that as the prediction for how many 16MHz pulses will be in the current high/low of the input signal. With a little math, I can get close enough to the angular postion I'm interested in. (Yes, it has to be real-time, no delay). However, this seemed very fpga/cpld real-estate expensive, given that it would likely involve a single cycle divide of some fairly wide bit-bus.

The hc4046 suggestion sounds interesting. I'll read some more on this beast and see if I can understand it.

The ideal circuit would look something like this:

Encoder Output ------- --|__|--| --> | C |-- \ | i |-- \ | r | . \ | c | . =-> 13 or 14 bit parallel position output | u | . / | i |-- / | t |-- / |-----|

Part of this circuit (the part to the right of the above definitely) will be implemented on an FPGA. So I was hoping there was an easy way to "multiply" the encoder output to 10x, feed that into counters of sorts (I need to match certain pulse counts, and trigger events in real-time according to these pulse counts).

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• posted

[...]

Both parts feed current mirror circuits inside the chip. The slight positive voltage subtracts from the voltage across the resistor and thus reduces the current in a nearly linear manner.

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