More on dual pulse generator

--- _________ Since you don't use the DISCHARGE output when you're running a 50% duty cycle 7555 astable, you can use it as the inverted version of the output by pulling it up to Vcc, so it looks like the transistor inverter can go away as well.

--
John Fields

--
No, you can\'t; they\'re in phase.  Sorry.

(See thread " Special "dual" pulse generator circuit " and "Porblems with NTE3083(4N32)" for recent discussion on this project)

I have now modfied my circuit to trigger the pulse width setting 555s on the leading edge of the pulse from the decade counter. See the schematic at:

The current problem is that at SOME frequencies, as set by the triggering

555 (leftmost in the diagram), the pulse width of the outputs cannot be set any wider than the width of the pulse out of the 4017 decade counter. That is, the circuit is supposed to allow me to set the output pulse width from something less than 1 ms to 10 or 11 ms for triggering rates between 45 and 260 Hz coming out of the decade counter. Sometimes it works, but at certain freqencies the pulse width is limited to the pulse width th the decade counter output pins. For example, if I set the frequency low, e.g., 50Hz, and then set the pulse width of the channel 1 output (upper signal flow path in the diagram) to some high value, e.g., 10 ms, then slowly increase the frequency the output pulse width will decrerease, dropping off to 3.8 ms at 260 Hz. Channel 2 appears to be OK at low and high frequencies, but at certain intermediate frequencies the pulse width does change with frequency. None of this should happen; the pukse width should be rock solid as frequency is changed.

I find this very strange, and cannot see why this is happening. I have looked at the signals at points all along both paths and things look pretty much as I would expect. For example, the the output pulses at the decade counter are correct for the set frequency, and the triggering pulse at pin 2 of both pulse width setting

555s is about 0.2 to 0.3 ms. The problem appears at pin 3 of the pulse width setting 555s. It appears that this voltage is sometimes getting pulled back to 0 at the end of the decade counter pulse, rather than the time determined by the 555 RC product.

Any suggestions?

TIA

Ed

Try decreasing the length of the output pulser by making the cap coming out of the 4017 smaller, say 62nF. That should decrease the trigger pulse coming into the 555 to something smaller than the output pulse you are after. Also, I don't think you need that 5.1k resistor on the output of the 4017.

Another thing is that the resistor/capacitor you are using for the timing element in the right most 555s are pretty big. They require the

555 to sink alot of current when the trigger occurs. You could scale them both down to 100th of their values, and the timing should be OK, but the 555 will have to sink alot less charge to trigger.

Neither of these may fix the problem, but they may give you more information about what is happening.

--
Regards,
   Robert Monsen

"Your Highness, I have no need of this hypothesis."
     - Pierre Laplace (1749-1827), to Napoleon,
        on why his works on celestial mechanics make no mention of God.

That can't happen. The capacitor, fixed resistor and pot at the astable 555 have been selected to limit the frequency between about 44 Hz and 270 Hz. The decade counter outputs are 1/10 of that frequency, 4.4 to 27 Hz. At 4.4 Hz the period is 227 ms, and at 27 Hz it is 37 ms. The capacitors and pots on the monostable 555s are selected to limit pulse widths between about 0.3 ms and 11 ms. Consequently, I should be able to get the full output pulse width at any allowed frequency. So that's not the problem.

I have no doubt that it would work, but unles there is something fundamentally wrong with the circuit I have implemented I'm not inclined to start over. I believe my problems have to do with the details, and my inexperience with design of circuits, not the fundamental design. If this is indeed the case, I expect I'd have similar problems with the new approach. I admit that there might be fewer if the component count could be reduced.

But you raise an interesting point regarding direct use of the 555 outputs to drive the optos. Are you saying to just ground pin 2 of the optos and hook pin 1 to the output of the 555?

I very much appreciate your comments.

Ed

Er, rather, scale down the capacitor, scale up the resistor...

--
Regards,
   Robert Monsen

"Your Highness, I have no need of this hypothesis."
     - Pierre Laplace (1749-1827), to Napoleon,
        on why his works on celestial mechanics make no mention of God.

--- Well, let's see...

Using

1.44 f = ------------ (Ra + 2rB)C

for the astable, I get fmax = 411Hz = 2.4ms, and fmin = 61.3Hz = 16.3ms,

so, the input to and outputs from your 4017 will look something like this:

_ _ _ _ _ _ _ _ _ _ _ _ _ CP _|1|_|2|_|3|_|4|_|5|_|6|_|7|_|8|_|9|_|0|_|1|_|2|_|3|_

|| |___ |___ Q1 _| |___________________________________| |_______ ->| || || |I believe my problems have to do with the details, and my inexperience

--- Reduced to three timers, a transistor, and some passives, so that lets you get rid of the 4017, three transistors, and some passives.

Basically, you'd wind up with a two chip (7555,556) solution!

---

--- Essentially, yes. You'd still need the current limiting resistor in there, but you could get rid of the two bipolars.

---

--- You're welcome.

Just for grins, I'll post the schematic to abse sometime today. I'll probably go ahead and build it too. I've got all the parts and it sounds like a fun project for a slow Sunday. If I do, I'll post pictures and waveforms on abse.

-- John Fields

--
Got the design and the schematic done, :-)  but I didn\'t build or
simulate it yet. :-( 

It\'s at abse as "More on dual pulse generator".

Hey, John, come on now! This is my project! But, since I can't stop you, maybe I ought to ask what is abse? Just in case I want to peek, you understand. No way I'm gunna copy you!

As for me, I've concluded there is an electronic conspiracy afoot. Now matter how I trigger the 555 off the 4017 there is this weird effect of the 4017 pulse width limiting the 555 pulse width. I set up one of the 555s on a separtate board to try out some of Robert Monson's ideas. Whether the coupling is through a cap or just resistance the unwanted effect is there.

What is it that could be causing the 555 to ignor it's RC time constant and obey instead the width of the 4017 pulse, even if all it sees of it is the effect of its leading edge on a capacitor?

Ed

--- Here's a SWCad schematic for my version you can look at and run if you want to download their free simulator. It's at:

Version 4 SHEET 1 1460 1192 WIRE -704 -384 -704 -624 WIRE -704 -688 -464 -688 WIRE -704 -320 -704

-288 WIRE -464 -752 -800 -752 WIRE -800 -752 -800 -288 WIRE -800 -288

-704 -288 WIRE -704 -288 -704 304 WIRE -704 -688 -704 -864 WIRE -704

-864 -128 -864 WIRE -128 -864 -128 -624 WIRE -128 -624 -240 -624 WIRE

-240 -752 -176 -752 WIRE -800 -784 -800 -752 WIRE -800 -864 -800 -928 WIRE -800 -928 -16 -928 WIRE -16 -928 -16 -752 WIRE -240 -688 -64 -688 WIRE 192 -688 192 -752 WIRE -16 -928 192 -928 WIRE 192 -928 192 -832 WIRE 192 -688 256 -688 WIRE 320 -688 400 -688 WIRE 400 -688 400 -752 WIRE 192 -928 400 -928 WIRE 400 -928 400 -832 WIRE 400 -928 528 -928 WIRE 528 -928 528 -832 WIRE 400 -688 528 -688 WIRE 528 -688 528 -768 WIRE 528 -688 736 -688 WIRE 528 -928 1040 -928 WIRE 1040 -928 1040

-752 WIRE 1040 16 960 16 WIRE 960 -752 1040 -752 WIRE 1040 -752 1040 -480 WIRE 736 -752 656

-752 WIRE 656 -752 656 -448 WIRE 656 16 736 16 WIRE 736 80 528 80 WIRE 192 80 192 16 WIRE 192 -160 192 -64 WIRE 192

80 256 80 WIRE 320 80 400 80 WIRE 400 80 400 16 WIRE 192 -160 400 -160 WIRE 400 -160 400 -64 WIRE 400 -160 528 -160 WIRE 528 -160 528 -64 WIRE 400 80 528 80 WIRE 528 80 528 0 WIRE 528 -160 1040 -160 WIRE 1040 -160 1040 16 WIRE 192 80 192 144 WIRE 80 192 128 192 WIRE 0 192 -64 192 WIRE -64 192 -64 -688 WIRE -64 -688 192 -688 WIRE 656 16 656 304 WIRE 656 304 400 304 WIRE -704 304 -704 416 WIRE 192 240 192 304 WIRE 192 304 -704 304 WIRE 736 -624 544 -624 WIRE 464 -624 400 -624 WIRE 400 -624 400 -384 WIRE 400 -384 656 -384 WIRE 656 -384 656 16 WIRE 736 144 544 144 WIRE 464 144 400 144 WIRE 400 144 400 304 WIRE 400 304 192 304 WIRE 960 -688 1168 -688 WIRE 1168 -688 1168 -624 WIRE 960 -624 1168 -624 WIRE 1168 -624 1168 -576 WIRE 1040 -928 1168 -928 WIRE 656 -448 1168 -448 WIRE 656 -448 656 -384 WIRE 1168 -448 1168

-512 WIRE 1184 304 1184 240 WIRE 1040 -208 1184 -208 WIRE 1040 -208

1040 -160 WIRE 656 304 1184 304 WIRE 960 80 1184 80 WIRE 1184 80 1184 144 WIRE 960 144 1184 144 WIRE 1184 144 1184 176 WIRE -704 -624 -672 -624 WIRE -592 -624 -576 -624 WIRE -496 -624 -464

-624 WIRE -704 -624 -704 -688 WIRE 1168 -928 1168 -896 WIRE 1168 -720

1168 -688 WIRE 1168 -816 1168 -800 WIRE 1184 -208 1184 -160 WIRE 1184

-80 1184 -48 WIRE 1184 32 1184 80 WIRE -464 -560 -496 -560 WIRE -496

-560 -496 -432 WIRE -496 -432 -176 -432 WIRE -176 -432 -176 -752 WIRE

-176 -752 -16 -752 WIRE 736 -560 704 -560 WIRE 704 -560 704 -480 WIRE

704 -480 1040 -480 WIRE 1040 -480 1040 -208 WIRE 736 208 704 208 WIRE 704 208 704 272 WIRE 704 272 1040 272 WIRE 1040 272 1040 16 FLAG -704 416 0 SYMBOL res -576 -640 R90 WINDOW 0 68 62 VBottom 0 WINDOW 3 70 63 VTop 0 SYMATTR InstName R1 SYMATTR Value 1e6 SYMBOL Misc\\\\NE555 -352 -656 R0 WINDOW 0 -98 -175 Center 0 WINDOW 3

-78 -149 Center 0 SYMATTR InstName U1 SYMBOL cap -720 -384 R0 WINDOW 0 30 4 Left 0 WINDOW 3 27 61 Left 0 SYMATTR InstName C1 SYMATTR Value .1¦ SYMBOL voltage -800 -880 R0 WINDOW 0 -74 53 Left 0 WINDOW 3 -76 24 Left 0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value 12 SYMBOL Misc\\\\NE555 848 -656 R0 WINDOW 0 -94 -182 Center 0 WINDOW 3 -79

-153 Center 0 SYMATTR InstName U2 SYMBOL Misc\\\\NE555 848 112 R0 WINDOW 0 -97 -180 Center 0 WINDOW 3 -79

-153 Center 0 SYMATTR InstName U3 SYMBOL res 176 -848 R0 SYMATTR InstName R4 SYMATTR Value 1k SYMBOL cap 320 -704 R90 WINDOW 0 49 63 VBottom 0 WINDOW 3 50 66 VTop 0 SYMATTR InstName C2 SYMATTR Value .1¦ SYMBOL res 384 -848 R0 SYMATTR InstName R5 SYMATTR Value 10k SYMBOL diode 544 -768 R180 WINDOW 0 -47 29 Left 0 WINDOW 3 -75 -6 Left

0 SYMATTR InstName D1 SYMATTR Value 1N4148 SYMBOL npn 128 144 R0 SYMATTR InstName Q1 SYMATTR Value 2N4401 SYMBOL res 176 -80 R0 SYMATTR InstName R6 SYMATTR Value 10k SYMBOL cap 320 64 R90 WINDOW 0 56 59 VBottom 0 WINDOW 3 51 63 VTop 0 SYMATTR InstName C3 SYMATTR Value .1¦ SYMBOL res 384 -80 R0 SYMATTR InstName R7 SYMATTR Value 10k SYMBOL diode 544 0 R180 WINDOW 0 -40 32 Left 0 WINDOW 3 -72 0 Left 0 SYMATTR InstName D2 SYMATTR Value 1N4148 SYMBOL res 96 176 R90 WINDOW 0 -34 56 VBottom 0 WINDOW 3 -33 59 VTop 0 SYMATTR InstName R2 SYMATTR Value 10k SYMBOL res 560 -640 R90 WINDOW 0 62 59 VBottom 0 WINDOW 3 60 55 VTop 0 SYMATTR InstName R3 SYMATTR Value 1000 SYMBOL res 560 128 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R8 SYMATTR Value 1000 SYMBOL res 1152 -816 R0 SYMATTR InstName R9 SYMATTR Value 274 SYMBOL cap 1152 -576 R0 SYMATTR InstName C4 SYMATTR Value .1¦ SYMBOL res 1168 -176 R0 SYMATTR InstName R10 SYMATTR Value 100k SYMBOL cap 1168 176 R0 SYMATTR InstName C5 SYMATTR Value .1¦ SYMBOL res -480 -640 R90 WINDOW 0 68 62 VBottom 0 WINDOW 3 69 56 VTop 0 SYMATTR InstName R11 SYMATTR Value 267k SYMBOL res 1152 -912 R0 SYMATTR InstName R12 SYMATTR Value 100k SYMBOL res 1168 -64 R0 SYMATTR InstName R13 SYMATTR Value 274 TEXT -674 256 Left 0 !.tran 0 .1s 0 .01s TEXT 1104 -856 Left 0 ;POT TEXT 1112 -112 Left 0 ;POT TEXT -664 -528 Left 0 ;POT

-- John Fields

On Mon, 06 Dec 2004 21:02:26 +0000, Terry Pinnell wrote:

--- Yup, thanks...

Version 4 SHEET 1 1592 1192 WIRE -704 -384 -704 -624 WIRE -704 -688 -464 -688 WIRE -704 -320 -704 -288 WIRE -464 -752 -800 -752 WIRE -800 -752 -800 -288 WIRE -800 -288 -704 -288 WIRE -704 -288 -704 304 WIRE -704 -688 -704 -864 WIRE -704 -864 -128 -864 WIRE -128 -864 -128 -624 WIRE -128 -624 -240 -624 WIRE -240 -752 -176 -752 WIRE -800 -784 -800 -752 WIRE -800 -864 -800 -928 WIRE -800 -928 -16 -928 WIRE -16 -928 -16 -752 WIRE -240 -688 -64 -688 WIRE 192 -688 192 -752 WIRE -16 -928 192 -928 WIRE 192 -928 192 -832 WIRE 192 -688 256 -688 WIRE 320 -688 400 -688 WIRE 400 -688 400 -752 WIRE 192 -928 400 -928 WIRE 400 -928 400 -832 WIRE 400 -928 528 -928 WIRE 528 -928 528 -832 WIRE 400 -688 528 -688 WIRE 528 -688 528 -768 WIRE 528 -688 736 -688 WIRE 528 -928 1040 -928 WIRE 1040 -928 1040 -752 WIRE 1040 16 960 16 WIRE 960 -752 1040 -752 WIRE 1040 -752 1040 -480 WIRE 736 -752 656 -752 WIRE 656 -752 656 -448 WIRE 656 16 736 16 WIRE 736 80 528 80 WIRE 192 80 192 16 WIRE 192 -160 192 -64 WIRE 192 80 256 80 WIRE 320 80 400 80 WIRE 400 80 400 16 WIRE 192 -160 400 -160 WIRE 400 -160 400 -64 WIRE 400 -160 528 -160 WIRE 528 -160 528 -64 WIRE 400 80 528 80 WIRE 528 80 528 0 WIRE 528 -160 1040 -160 WIRE 1040 -160 1040 16 WIRE 192 80 192 144 WIRE 80 192 128 192 WIRE 0 192 -64 192 WIRE -64 192 -64 -688 WIRE -64 -688 192 -688 WIRE 656 16 656 304 WIRE 656 304 528 304 WIRE -704 304 -704 416 WIRE 192 240 192 304 WIRE 192 304 -704 304 WIRE 736 -624 592 -624 WIRE 656 -448 656 -304 WIRE 960 -688 1168 -688 WIRE 1168 -688 1168 -624 WIRE 960 -624 1168 -624 WIRE 1168 -624 1168 -576 WIRE 1040 -928 1168 -928 WIRE 656 -448 1168 -448 WIRE 1168 -448 1168 -512 WIRE 1184 304 1184 240 WIRE 1040 -208 1184 -208 WIRE 1040 -208 1040 -160 WIRE 656 304 1184 304 WIRE 960 80 1184 80 WIRE 1184 80 1184 144 WIRE 960 144 1184 144 WIRE 1184 144 1184 176 WIRE -704 -624 -672 -624 WIRE -592 -624 -576 -624 WIRE -496 -624 -464 -624 WIRE -704 -624 -704 -688 WIRE 1168 -928 1168 -896 WIRE 1168 -720 1168 -688 WIRE 1168 -816 1168 -800 WIRE 1184 -208 1184 -160 WIRE 1184 -80 1184 -48 WIRE 1184 32 1184 80 WIRE -464 -560 -496 -560 WIRE -496 -560 -496 -432 WIRE -496 -432 -176 -432 WIRE -176 -432 -176 -752 WIRE -176 -752 -16 -752 WIRE 736 -560 704 -560 WIRE 704 -560 704 -480 WIRE 704 -480 1040 -480 WIRE 1040 -480 1040 -208 WIRE 736 208 704 208 WIRE 704 208 704 272 WIRE 704 272 1040 272 WIRE 1040 272 1040 16 WIRE 1216 -400 896 -400 WIRE 816 -400 592 -400 WIRE 592 -400 592 -624 WIRE 656 -304 1216 -304 WIRE 656 -304 656 16 WIRE 736 144 592 144 WIRE 592 144 592 384 WIRE 592 384 832 384 WIRE 912 384 1232 384 WIRE 1232 480 528 480 WIRE 528 480 528 304 WIRE 528 304 192 304 WIRE 1168 -928 1440 -928 WIRE 1440 -928 1440 -544 WIRE 1440 -464 1440 -400 WIRE 1440 -400 1408 -400 WIRE 1184 -208 1472 -208 WIRE 1472 -208 1472 240 WIRE 1472 320 1472 384 WIRE 1472 384 1424 384 WIRE 1408 -336 1584 -336 WIRE 1584 -336 1584 448 WIRE 1584 448 1424 448 WIRE 528 480 528 560 WIRE 528 560 1584 560 WIRE 1584 560 1584 448 FLAG -704 416 0 SYMBOL res -576 -640 R90 WINDOW 0 68 62 VBottom 0 WINDOW 3 70 63 VTop 0 SYMATTR InstName R1 SYMATTR Value 1e6 SYMBOL Misc\\\\NE555 -352 -656 R0 WINDOW 0 -98 -175 Center 0 WINDOW 3 -78 -149 Center 0 SYMATTR InstName U1 SYMBOL cap -720 -384 R0 WINDOW 0 30 4 Left 0 WINDOW 3 27 61 Left 0 SYMATTR InstName C1 SYMATTR Value .1µ SYMBOL voltage -800 -880 R0 WINDOW 0 -74 53 Left 0 WINDOW 3 -76 24 Left 0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value 12 SYMBOL Misc\\\\NE555 848 -656 R0 WINDOW 0 -94 -182 Center 0 WINDOW 3 -79 -153 Center 0 SYMATTR InstName U2 SYMBOL Misc\\\\NE555 848 112 R0 WINDOW 0 -97 -180 Center 0 WINDOW 3 -79 -153 Center 0 SYMATTR InstName U3 SYMBOL res 176 -848 R0 SYMATTR InstName R4 SYMATTR Value 1k SYMBOL cap 320 -704 R90 WINDOW 0 49 63 VBottom 0 WINDOW 3 50 66 VTop 0 SYMATTR InstName C2 SYMATTR Value .1µ SYMBOL res 384 -848 R0 SYMATTR InstName R5 SYMATTR Value 10k SYMBOL diode 544 -768 R180 WINDOW 0 -47 29 Left 0 WINDOW 3 -75 -6 Left 0 SYMATTR InstName D1 SYMATTR Value 1N4148 SYMBOL npn 128 144 R0 SYMATTR InstName Q1 SYMATTR Value 2N4401 SYMBOL res 176 -80 R0 SYMATTR InstName R6 SYMATTR Value 10k SYMBOL cap 320 64 R90 WINDOW 0 56 59 VBottom 0 WINDOW 3 51 63 VTop 0 SYMATTR InstName C3 SYMATTR Value .1µ SYMBOL res 384 -80 R0 SYMATTR InstName R7 SYMATTR Value 10k SYMBOL diode 544 0 R180 WINDOW 0 -40 32 Left 0 WINDOW 3 -72 0 Left 0 SYMATTR InstName D2 SYMATTR Value 1N4148 SYMBOL res 96 176 R90 WINDOW 0 -34 56 VBottom 0 WINDOW 3 -33 59 VTop 0 SYMATTR InstName R2 SYMATTR Value 10k SYMBOL res 912 -416 R90 WINDOW 0 62 59 VBottom 0 WINDOW 3 60 55 VTop 0 SYMATTR InstName R3 SYMATTR Value 1000 SYMBOL res 928 368 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R8 SYMATTR Value 1000 SYMBOL res 1152 -816 R0 SYMATTR InstName R9 SYMATTR Value 274 SYMBOL cap 1152 -576 R0 SYMATTR InstName C4 SYMATTR Value .1µ SYMBOL res 1168 -176 R0 SYMATTR InstName R10 SYMATTR Value 100k SYMBOL cap 1168 176 R0 SYMATTR InstName C5 SYMATTR Value .1µ SYMBOL res -480 -640 R90 WINDOW 0 68 62 VBottom 0 WINDOW 3 69 56 VTop 0 SYMATTR InstName R11 SYMATTR Value 267k SYMBOL res 1152 -912 R0 SYMATTR InstName R12 SYMATTR Value 100k SYMBOL res 1168 -64 R0 SYMATTR InstName R13 SYMATTR Value 274 SYMBOL Optos\\\\4N25 1312 -336 R0 SYMATTR InstName U4 SYMBOL Optos\\\\4N25 1328 448 R0 SYMATTR InstName U5 SYMBOL res 1424 -560 R0 SYMATTR InstName R14 SYMATTR Value 10000 SYMBOL res 1456 224 R0 SYMATTR InstName R15 SYMATTR Value 10000 TEXT -674 256 Left 0 !.tran 0 1s 0 .01s TEXT 1104 -856 Left 0 ;POT TEXT 1112 -112 Left 0 ;POT TEXT -664 -528 Left 0 ;POT

-- John Fields

Robert,

I tried leaving out the 5.1k in the triggering NPN. Could't get it to trigger that way, so I put it back and went to a 0.047 mF cap. Works, but same frequency dependency of pulse width.

Also went to a 100k pot and 0.1 mf cap at one of the pulse width setting

555s. Same problem.

In this regard, should I go to same configuration at the triggering 555, i.e., the leftmost one? The reason I ask is that while said before that the problem I'm having is that the pulse width is being limited to no more than the pulse width at the outputs of the 4017, I could as as well have said "limited to the period of the triggering 555, " leading me to wonder if there is a problem with they way I've configured it. Could it be that that 555 is somehow triggering a reset at the pulse width

555s, e.g., via RF or ground coupling?

Ed

I just had another thought (dangerous, I know... ;).

The transistions of the 4017 could be affecting the 555, causing it to trigger improperly. Try a 1uF cap between the Vcc and GND pins of the

4017, and another between the power and ground pins of the 555. They have to be close to the chips (preferably right between the pins).

If this is true, you can probably see it by scoping the power rail.

What happens is that when the cmos gates in the 4017 change state, they can bounce the power if it isn't very stiff. This will cause other chips near it to malfunction. The 555 also has this problem, sucking power during transitions.

--
Regards,
   Robert Monsen

"Your Highness, I have no need of this hypothesis."
     - Pierre Laplace (1749-1827), to Napoleon,
        on why his works on celestial mechanics make no mention of God.

Yes, see my other post.

--
Regards,
   Robert Monsen

"Your Highness, I have no need of this hypothesis."
     - Pierre Laplace (1749-1827), to Napoleon,
        on why his works on celestial mechanics make no mention of God.

etc

I think your copy/paste was scrambled. I'm no LT Spice expert, but for example I reckon all those WIRE lines should have a syntax like this: WIRE -704 -384 -704 -624 WIRE -704 -688 -464 -688 etc IOW, 1 per line, 4 co-ordinates each, ending with a Return character.

Running it as it stands gives error: "Unknown schematic syntax".

--
Terry Pinnell
Hobbyist, West Sussex, UK

If I put the scope on the power rail and set it AC I see sort of a square wave. It has a peak-to-peak of 4-5 mV and the same period as the triggering 555!

Does this mean the caps should be between the VCC and GRD pins of the 555 as well as the 4017, or instead of at teh 4107, or both?

I'm off to the electronics store to get come 1uF caps.

Ed

Schematic now looks fine - a lot easier on the eye than

--
Terry Pinnell
Hobbyist, West Sussex, UK

I took the IC components back to the breadboard so I could make changes easier. When I changed the input harness to the trirgering 555, multiplying all resistors by 100 and dividing the capacitor by 100 the power rail voltage became clean. However, the bad behavior continued.

Nonetheless, I put the 1 mF cap between pins 15 & 16 on the 4017 and the bad behavior went away! The pulse width is completely independent of the triggering frequency. The circuit now works with purely resistive coupling at the base of the NPN transistor, and the RESET pin of the pulse width setting 555 tied to PIN 2, or with an 0.047 mF capacitor and RESET tied to +12.

Thanks, Robert. You nailed it!

One other question. My original circuit used 10 mF caps and 1k pots in the input harnesses of the 555s, probably because the first 555 example I saw did it that way. But as has been pointed out here, I could as well have used smaller caps and larger pots (and other resistors) to get the same timings, and lower currents. As mentioned above, this cleans up the power rail voltage. May I assume that this is, in general, better practice?

Ed

(You really need to start bottom posting. Thats the convention here, and it makes it easier for everybody to read the replies)

Are you talking about microfarad or millifarad caps? mF = millifarad which is 1000x uF.

With larger resistors and smaller caps, there is far less charge and thus current when it discharges. This causes less problems like the one you were seeing. However, there is a limit, which is that at some point, the leakage through the 555 may cause errors, leading up to it not working at all.

The best advice I can give you is to read the datasheet. They understand their device, and can give you advice based on their testing and theoretical knowledge. Learning how to read datasheets is the best thing you can do to learn how to use any chip.

--
Regards,
   Robert Monsen

"Your Highness, I have no need of this hypothesis."
     - Pierre Laplace (1749-1827), to Napoleon,
        on why his works on celestial mechanics make no mention of God.