pulse is "far too long" doesn't cut it. At your clock frequency the final stage outputs are supposed to be high for 100 seconds, and they're supposed to last high until the next clock pulse comes along. How long are they high now and how long do you want them to stay high? It may have been the rats nest was in error, it's really easy to get unwanted cross-coupling into inputs with messy wiring, so the last stage in the rats nest could be getting double triggered on its clock input.
chips work. I'd assumed the pulse duration (the ON state)would remain the same throughout the chain of 4017s and that only the OFF time *between* them would increase. Clearly from what you say that's not what happens. So basically if I want to end up with say one, one second long 'high' on the final output after a delay of 7 days (for example) I need to back calculate so the first pulses from the 555 have a much shorter ON duration than 1 second. That's what your suggested mod is designed to do, I guess? I can see that now. Many thanks for the clarification.
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True, but I don't think that's what you want since all that looks like
is a Johnson counter with more outputs than a single 4017.
If you're looking to output a single pulse as wide as your clock,
after a long delay, then you'll need to do it using a different
counter.
OK. Thanks for the datasheet link. The sheets I've seen up until now have b een very terse affairs, badly photocopied and hard to see. This one is way more informative. I'm not in a position to post a schematic at this time, but from what you s aid in your last post it wouldn't assist much if the chips I'm using are wr ong.
Basically all I want to do is make up a time-lock for a cash safe. After a
7 day delay during which the safe remains locked shut, one timed pulse of 1 second releases its electromagnetic lock and the safe can be opened. Obvio usly that pulse if it's from CMOS will need to be beefed up to actuate the lock, but that's the easy bit. Why are 4017s not suitable for the timing part of the application?
very terse affairs, badly photocopied and hard to see. This one is way more informative.
in your last post it wouldn't assist much if the chips I'm using are wrong.
day delay during which the safe remains locked shut, one timed pulse of 1 second releases its electromagnetic lock and the safe can be opened. Obviously that pulse if it's from CMOS will need to be beefed up to actuate the lock, but that's the easy bit.
--- Now that we know your application, the 4017's can be used successfully by treating them like decade counters and decoding the outputs to correspond to the seven day delay.
Since there are 604800 seconds in seven days, you'll need six counters hooked up like this: (View using a fixed-pitch font)
So what happens is that when the counter chain gets to 604800, the output of the HC30 will go low, triggering the 555, which is where your lock-unlatching pulse comes from, with its width being totally independent of the clock pulse's.
I'd be a little careful about what I used for the 1Hz source, since with just a 1% error there'll be about a +/- 2 hour window when the latch will let go.
4017 into the input of the next with no pull-down resistors at all; never occurred to me that might be necessary, quite honestly. I'll modify accordingly. Hopefully that might fix that aspect of the problem.
An excellent digital guru buddy of mine _always_ ties unused inputs thru resistors. Need to test/debug something, it makes it easy to insert extra signals. ...Jim Thompson
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I love to cook with wine. Sometimes I even put it in the food.
e been very terse affairs, badly photocopied and hard to see. This one is w ay more informative.
u said in your last post it wouldn't assist much if the chips I'm using are wrong.
a 7 day delay during which the safe remains locked shut, one timed pulse o f 1 second releases its electromagnetic lock and the safe can be opened. Ob viously that pulse if it's from CMOS will need to be beefed up to actuate t he lock, but that's the easy bit.
Many thanks, John! I haven't studied your circuit in detail yet, so may have to ask for clarif ication on a few things, but it sounds good by your description. I'm not th e least concerned with a 1% error; it can be out by up to 12hrs either way as far as I'm concerned and would still be absolutely fine for my purposes.
Very good point- one of the most accurate long duration timebases available for applications like this is the power line. You should get +/- a few seconds accuracy over a seven day interval. The OP really needs something like this:
formatting link
There he has provisions for battery backup and external crystal timebase to coast through black/brown-outs. It can't miss. The drawback is it needs a controller, but it's worth the effort for the vastly improved performance over what he has now.
for applications like this is the power line. You should get +/- a few seconds accuracy over a seven day interval. The OP really needs something like this:
formatting link
coast through black/brown-outs. It can't miss. The drawback is it needs a controller, but it's worth the effort for the vastly improved performance over what he has now.
Thanks, but it's way too much for my modest requirements. JF's design should do nicely if I can get it up and running.
clarification on a few things, but it sounds good by your description. I'm not the least concerned with a 1% error; it can be out by up to 12hrs either way as far as I'm concerned and would still be absolutely fine for my purposes.
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I tried to simulate the circuit and it seems that something is very
wrong.
I'll see if I can find out what the problem is and post back when I
do.
Sorry 'bout that. :-(
rification on a few things, but it sounds good by your description. I'm not the least concerned with a 1% error; it can be out by up to 12hrs either w ay as far as I'm concerned and would still be absolutely fine for my purpos es.
Thanks very much, John. I'm sure a man of your caliber won't struggle too m uch to get to the root of the problem, whatever it is. I've already ordered the NAND gat chip but haven't laid out a new board yet, so no harm done! : ) I'll be interested to read your findings in due course...
rification on a few things, but it sounds good by your description. I'm not the least concerned with a 1% error; it can be out by up to 12hrs either w ay as far as I'm concerned and would still be absolutely fine for my purpos es.
You want to use Q0 of each counter to clock the succeeding stage and not Q9 . A rising edge on Q0 of any single stage means it has received ten clocks, so that is the time to increment the next decade by one. You probably want to include a manual MR input too. Maybe not a bad idea to add some filteri ng to the 555 trigger to avoid false triggering due to decoding hazards by the '30.
larification on a few things, but it sounds good by your description. I'm n ot the least concerned with a 1% error; it can be out by up to 12hrs either way as far as I'm concerned and would still be absolutely fine for my purp oses.
Q9. A rising edge on Q0 of any single stage means it has received ten clock s, so that is the time to increment the next decade by one. You probably wa nt to include a manual MR input too. Maybe not a bad idea to add some filte ring to the 555 trigger to avoid false triggering due to decoding hazards b y the '30.
You could use the CARRY_OUT too, same difference, the leading edges are coi ncident.
On Wednesday, 12 December 2012 23:41:32 UTC+1, snipped-for-privacy@gmail.com wr ote:
clarification on a few things, but it sounds good by your description. I'm not the least concerned with a 1% error; it can be out by up to 12hrs eith er way as far as I'm concerned and would still be absolutely fine for my pu rposes.
t Q9. A rising edge on Q0 of any single stage means it has received ten clo cks, so that is the time to increment the next decade by one. You probably want to include a manual MR input too. Maybe not a bad idea to add some fil tering to the 555 trigger to avoid false triggering due to decoding hazards by the '30.
oincident.
Thank you for your interest, Fred. The more the merrier. John, if you could post the LTSpice netlist for your suggested circuit that would be very helpful to my understanding at this end. Thanks again.
have been very terse affairs, badly photocopied and hard to see. This one is way more informative.
you said in your last post it wouldn't assist much if the chips I'm using are wrong.
a 7 day delay during which the safe remains locked shut, one timed pulse of 1 second releases its electromagnetic lock and the safe can be opened. Obviously that pulse if it's from CMOS will need to be beefed up to actuate the lock, but that's the easy bit.
Oh my. Hitting a one second window once a week is very difficult in human operated systems. Perhaps you may wish to be more thoughtful about your design requirements.
All in all this application begs for a micro-controller based solution.
day delay during which the safe remains locked shut, one timed pulse of 1 second releases its electromagnetic lock and the safe can be opened. Obviously that pulse if it's from CMOS will need to be beefed up to actuate the lock, but that's the easy bit.
For large counts chips like 4060 and 4040 may be easier to use
A 4060 running with the oscillator running at 16Hz will produce 1hz pulses on pin 7 and a period of 1024 seconds on pin 3 A week is 604800 seconds so you need to divide that rate by 590 Which can probably be done using a diode-and and a 4040 counter. A D-type flip-flop to mix that with the 1hz rate to get the 1 second pulse and another flip-flop to halt the circuit after that. If you can live with slightly wider pulses to the output you can use a divide bt 512 instead of 590 which is easier to arrange using these binary counters.
if you need more precision than the R-C oscillator at the input can provide perhaps you can use the frequency of the AC supply.
Too unnecessarily complicated for my modest purposes, I'd say. That's why I'd like to stick to something close to the original concept. The circuit John Fields posted, if it can be fixed-up, would be close to ideal for me.
I had considered this. Sniff some mains inductively, then pass it through a rectifier and an inverter/Schmidt trigger to convert it to a square wave a nd then count the pulses up to a pre-determined limit. Accurate for sure, b ut not being terribly au fait with what chips are out there I don't know of an IC that could count up to 604,800 decimal and put out a signal pulse wh en that target has been reached. I'd still rather stick with JF's design...
a rectifier and an inverter/Schmidt trigger to convert it to a square wave and then count the pulses up to a pre-determined limit. Accurate for sure, but not being terribly au fait with what chips are out there I don't know, of an IC that could count up to 604,800 decimal and put out a signal pulse when that target has been reached. I'd still rather stick with JF's design ...
Sorry, that should have been 604,800 x 50 from a 50Hz mains source...
rectifier and an inverter/Schmidt trigger to convert it to a square wave and then count the pulses up to a pre-determined limit. Accurate for sure, but not being terribly au fait with what chips are out there I don't know, of an IC that could count up to 604,800 decimal and put out a signal pulse when that target has been reached. I'd still rather stick with JF's design...
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That's 30,420,000 pulses, easily done with 2 HC4020s and an HC30
Thanks for the update, John. Nice to hear you didn't have to do any further mods on it. After a great deal of fruitless searching my ISP has informed me they no longer provide access to alt.binaries hierarchy and couldn't or wouldn't give me a reason! The netlist is just ascii so could you post it h ere, perhaps? TIA.
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