These are (iirc) 5 Gb/s lines, with forward error correction, adaptive thresholds, preemphasis, decision feedback equalization, yada yada yada. The whole thing is tweaked right to the eyeballs, but it meets a
5-nines availability spec (5 minutes down time per year).Cute gizmos, but all that stuff costs power and latency, which is another reason for going optical. We need to get below 100 uW/(Gb/s) (100 fJ/bit), which is going to be a challenge.
Cheers,
Phil Hobbs
That's what I thought you were thinking of doing.
I did a bit of handwaving. Xiling pads have a lot of input capicatance and the pullups have a lot of slop in the specs.
The Spartan3 data sheet I just glanced at said 3 to 10 pF and 0.8 to 2.3 mA for the pullups (at 3.3V)
If we assume a pin only goes to one other pin with roughly the same capicatance and the trace is a few inches (at 2 pF per inch) that's roughly a 3:1 change between making contact and no contact. More for a long trace, less if the other pad has lower input capicatance.
I'd probably assume that the pullups on a chip are all roughly the same and run a calibration pass, and then run the real scan.
It might take more than that, say calibration on a known good board to measure the other chip and length of the trace.
Moving the power to another connector doesn't help your signal integrity.
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