Hi every one
i m doing a project i.e. implementation of FIR filter in Verilog environment ..... for FPGA applications... well in that i have to synchronise the verilog code with the sampling period of ADC ... but i m not able to do so..having some problems...can any one help me.... how to adjust the clock of verilog with that of the ADC period?? can any one suggest me some good stuff to get the concepts correct ?
thanx in advance bye for now Mona
To be honest, synchronising to an external data source is not particularly difficult (although the implementation needs care).
Using an external ADC that provides a 'done' signal is the easiest method. You may then synchronise to that signal (by qualifying the code against it) remembering to take care because it comes from an asynchronous domain. You could also use a FSM quite simply for this purpose.
Cheers
PeteS
Thanx Petes for reply...
u right ...i m taking ADC output using matlab... the prob is i m not getting the correct output from verilog code..although the logic is correct...so i guess the clock of verilog is needed to be adjust..but i m not able to do so :( hope u got my point... plzzz help me
thanx bye Mona
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