I'm working on a XUP-V2Pro project which needs both the VDEC-1 video capture card and a 256-MB memory module. The Base System Builder produced a UCF file that have these lines:
Net fpga_0_DDR_CLK_FB LOC=C16; Net fpga_0_DDR_CLK_FB IOSTANDARD = SSTL2_II; Net fpga_0_DDR_CLK_FB_OUT LOC=G23; Net fpga_0_DDR_CLK_FB_OUT IOSTANDARD = SSTL2_II;
Digilent's Video Capture sample has this:
NET "LLC_CLOCK" LOC = "B16" | IOSTANDARD = LVCMOS25 ; NET "LLC_CLOCK" PERIOD = 25 ns;
All three of these pins are in bank 0; this causes the tools to produce this error:
ERROR:Place:311 - The IOB LLC_CLOCK is locked to site PAD55 in bank 0. This violates the SelectIO banking rules. Other incompatible IOBs may be locked to the same bank, or this IOB may be illegally locked to a Vref site.
The design builds if I change LLC_CLOCK to SSTL2_II, but I don't know if this will work reliably (I'm not familiar with SSTL2_II). Did whomever designed the XUP really place incompatible IO standards on bank 0? Is there a good way around this error?
Todd