Xilinx ML40x VGA Documentation

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I am looking for further documentation for the VGA connections on the ML40x

ug82 says that there is 50MHz chips on the ML401s and 140MHz chips on the
ML402s and ML403s.  The ML403's FX12 has reduced pins and only five bits per
color.  I suppose the best VGA would therefore come from the ML402s.

From the schematic I see that the upper five bits per color are attached to
Bank6 and the lower three bits per color are attached to Bank9.  There is a
difference in drive voltage between the two banks, does the VGA chip care?
Is there anyway to compensate with different drive currents.

I have a few UCF files with different stories. What does contingent mean in
a UCF file?

Is there any other documents other than the Xilinx schematics and the VGA
manufacturers data sheets?

Brad Smallridge

Re: Xilinx ML40x VGA Documentation
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the video dacs clock the data so as long as setup and hold times are met the
banks for the DAC outputs should not be an issue. so the vga chip does not


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