ML403 - Virtex4 XC4VFX12 - PPC405 - Xilinx EDK V10.1
Hi,
I have a working PPC405 design to which I want to add the APU FPU IP (enough acronyms?). I have used the wizard to configure basically the same design, but with the FPU included - this is therefore the default wizard hardware design with no manual tinkering from me on either the hardware or software libraries. This now runs non floating point instructions but generates program exceptions when an FPU instruction is executed.
Looking at the PPC405 block reference guide I am informed that I have to set bits 6 (APU present) and 18 (FCM floating point unit present) in the MSR register of the PPC405 in order for the APU to intercept the FPU instructions - but the PPC405 reference guide from Xilinx states that all these bits are unsupported and must be set to 0. This seems contradictory.
I have downloaded the reference design for the FPU from the Xilinx WEB site, but this seems to go into the weeds when executing a FLOP instruction too.
Any advice on how to add the APU FPU unit to a PPC405 design without FPU instructions generating exceptions would be gratefully received!