pausing execution on ppc405

Hello,

i'm trying to stop a running executable on the ppc405 placed on a virtex2-pro. Currently i'm trying to do this by pulling the clock-input (CPM405CLOCK) to the ppc to 1 (simple by using a multiplexed bufg switching between normal clock( ppc_clk_), and net_vcc0), thus imitating kind of power management as i read in the ppc405-block-reference-guide. This approach won't work, the ppc is not responding when normal clock operation continues. My next intention was to suspend the ppc in software, though there is no halt-instruction. In further threads i read setting the msr[13]-bit will put the ppc to sleep and certain interrupts will awaken it again. So, if anyone has done this before or has further suggestions how to do this any help would be very useful. Thanks.

Best regards, Patrick Siegel

Reply to
Patrick
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Depending on what you are trying to do you can use the DBGC405DEBUGHALT pin on the processor block to stop the processor. See the PowerPC 405 Processor Block Guide for more information

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- Peter

Patrick wrote:

Reply to
Peter Ryser

DBGC405DEBUGHALT

Hello,

thanks for the hint, i'll try. But i think i found out that solely stopping execution won't solve my problem. What i am trying to do is bypass the ppc to directly access sdram (a component on the fpga is saving/fetching data in sdram, but an executable is running in sdram, too. Resulting in concurrent accesses on the same addresslines ). My hope is, once the ppc is put to sleep, i can manage the bus and access sdram without destroying the executable/cpu-context. My first thought was to use DMA, but i cannot find any examples how to implement a DMA-capable obp-ipif with a master attachement to the bus, at least not with EDK6.2. (as far as i understand a master attachement is needed for dma-access) EDK6.2 only provides a very basic opb-ipif reference-design with a master attachement..

Best regrads Patrick

Reply to
mai99drh

^C in gdb over xmd over jtag?

-Tony

Reply to
tony.p.lee

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