Chirp generator / CORDIC algo ?

I hope you are aware that there are a number of high performance chips available for chirp generation. For example:

We might want to take a look at how they do chirp generation.

You could use a cordic algorithm, but you would need to "unroll" it (it is an iterative algorithm), I would not suggest doing that, though.

It sounds like you mean that your supervisor wants to store the entire chirp on the FPGA? Normally a better solution would be to store a sine lookup table on the FPGA, and implement a phase accumulator to drive it.

I am not sure what you mean about connecting the FPGA to a PC to use Matlab. I commonly generate a data file with Matlab, and then use a bit of C code to turn that into a VHDL package, which then gets compiled into the FPGA. However, that would only work in this case if there were only a couple possible chirps being used.

example:

Well to be honest, no i did not know :) My project is part of a much bigger one and some of the components seems (i have to get confirmation) to be imposed. Anyway, I'm also looking for the best solution I can make so this is the kind of proposition I will "study" carefully. Thank you !

Ok, so I think I going to forget Cordic :)

I will have confirmation soon about this aspect, it seems that this is not clear at the moment. But from what i understood, yes we are going to store the entire chirp signal in the FPGA. Normally, the FPGA does not have to generate the signal, he only has to use to data about it.

Yes, that's more about what you say. I don't think we are going to control Matlab by an FPGA :) The main idea is that the chirp will be done by Matlab and then the data from the computer will be send to the FPGA. So we will have a link between the PC and the FPGA. Since the FPGA is capable of doing calculation I just though we could forget the PC which will be a sort of "gain" in the project.

Thank you very much for your help and your ideas, I'm going to work on it to see what is possible in the context of my project :) The main idea for me is clearly to make the most of the Virtex V.

X

First of all, in something like a Virtex-5, you can easily achieve

200Msps for a chirp. I don't know that I would recommend CORDIC for creating a sine. It's no longer the most resource-efficient method for creating a sinusoid. A quarter-wave lookup in a 1024-deep Xilinx blockROM will give you 12 bits of phase resolution. You can augment that with a first-order Taylor correction if you needed more precision.

A chirp could be implemented with a DDS-type structure. A phase accumulator (NCO) would be connected to the sin/cos ROM. The phase increment in the phase accumulator would be a counter that would increase linearly to produce the chirp.

I'm not sure what Matlab solution you're talking about, but you could use Xilinx's SysGen. It has accumulator and quarter-wave sin/cos ROM blocks which you could wire together fairly quickly and test in the Matlab/Simulink environment. Although it might not yield the fastest implementation, it should get you 200Msps in a Virtex-5.

-Kevin

Actually, I meant that the phase increment would *decrease*, if you want to produce a rising chirp. -Kevin

Thank you very much for your help.

I will work on all ideas because I'm a beginner in all that, so I need time to understand everything :)

X

Basically your supervisor told you that the FPGA will be used to store an arbitrary waveform and to send it to the DAC. No math is supposed to be done in it. You are supposed to use MATLAB to design the waveform and then upload (or is it download? :)) it to the memory in the FPGA. The FPGA will then simply read it back with the DAC sample rate... If you don't need to change your waveform quickly and/or you need to be able to "play back" some other waveforms then it is the way to go. Otherwise you could drop the MATLAB part and design your own hardware chirp generator as Kevin described.

/Mikhail

The Matlab could be (and maybe will be) the best solution but in fact we will have different chirps to generate. This solution is dependent to a computer. I will explore the DDS idea and see if I can do it and if we can meet all the requirements.

Xavier

As I need to develop this solution in about 4 months, all the people on the project advice me to use the matlab idea because it's the easiest to have the work done within the deadlines. There are no longer problem with a PC Link because the FPGA boards have a embedded Flash memory where i will be able to save the datas.

I still be curious about the lookup table because as I told you I don't have any experience in all that. Do you have any information (links or book references) about this method ? I have at the moment no idea about the memory I will need for all the chirps, so it could be a good solution.

Finally, even if it's maybe not the "philosophic" way of doing it, what do you think about storing all the datas we need (different chirps) and just using the FPGA to generate the signal at the speed wanted ?

Xavier

In this case the lookup table has a phase input of however many bits of resolution you determine you need, and a sine output of the number of bits for your ADC, divided by 4 because you only need one quadrant of the sine.

Take a look at the diagram of the AD9858 to see how this is done. You start with an accumulator that accumulates frequency. It will be loaded with the starting frequency, and then on every frequency step (possibly less than your 200MHz), the frequency will increment by a constant amount. That is, the input to the accumulator is your frequency sweep step size (aka sweep rate).

The output of that goes to the input of the phase accumulator. This probably operates at your 200MHz. You will need to have a large number of bits in the phase accumulator to get good accuracy.

The upper bits of the output of the phase accumulator goes to the sine lookup table; the "phase to amplitude conversion" block in the AD9859 diagram.

You can easily model this in Matlab, and determine how many bits you will need at each stage for your design.