Virtex 5 announced

The $0.00 price was a TBD placeholder until the final price is set. The selling price for both of the boards will be in $1000-$1500 range. As with all of the Prototyping Platforms, these boards do not ship with a specific part. I know that this may seem unusual and undesirable, but these are meant to be used across any of the devices that come in a specific package type for prototyping purposes and the user supplies the device that they want to use.

They should be shipping in early July.

Ed McGettigan

-- Xilinx Inc.

Kudos on the new release!

But I started to glaze over as you turned on your marketing engines. I sincerely prefer the technical Austin.

Way to go, Xilinx.

- John_H

yada yada

Antti schrieb:

Hmm. There really is no difference between a MUX and a LUT. Same schematic symbol, same choice of implementations, same thing.

You can not really read the circuit speed from the datasheet or FPGA editor, as they use abstracted timing models. You can push delay around almost at will in a timing model. At any node of the timing model you can subtract a delay from all outgoing edges and add them to all incoming edges without changing the model. If you reduce the delay of some edges to zero you can merge nodes. You can even have negative delay edges in timing models.

You can use this to simplify the model for your software or for the user. Or you can try to look better than your competitor this way because people tend to compare certain delays and ignore others.

As a note: The value for the carry chain is pretty reliable beacuse each element is immediately preceeded and succeeded by an identical element. Not much pushing possible there.

Kolja Sulimma

!

than

The Virtex-5 6-input LUT is a true 64-bit look-up-table. Any 6 input function can be implemented in the LUT. You can of course think of any LUT as being generated a 128-to-1 MUX, but that would be inefficient in actual hardware to build.

As for the timing, the Virtex-5 data sheet is online with timing delays for all three speed grades so you can verify the performance differences.

Ed McGettigan

-- Xilinx Inc.

snipped-for-privacy@rcn.com schrieb:

Not really. There were competitors with larger and smaller LUTs twelve years ago. There has been anything from seas of AND gates over 2-LUTs up to 6-LUTs. Until now 4-LUTs had by far the most success.

Larger LUTs also means fewer LUTs and slower LUTs. The area of a LUT increases exponentially with the number of inputs and as the LUTs grow, more and more inputs can't be used on avarage.

Research in the early ninetees suggested that 3-LUTs are better than

4-LUTs because there are so many adders in modern designs. The addition of dedicated carry logic moved the sweet spot over to 4-LUTs.

The move to larger LUTs now is probably trigger by wiring: The relative wiring delay is increasing dramatically for smaller technologies so that it becomes more important to minimize the interconnect than to minimize LUT delay. Areawise Xilinx chose to support designs with a rather high rent exponent. Therefore the larger circuit densities require a larger amount of wiring. It probably turned out that after filling the chip with wires and layouting the logic and configuration storage below there was a significant amount of silicon area left under the wires. In that situation blowing up the LUTs comes for free area wise.

Kolja Sulimma

Austin Lesea schrieb:

So what is recommended if I want to use the MGTs, perhaps @ 6.3 Gbit/s

Virtex-II ProX or V4 ?

Are the Virtex-II ProX already available and how is the user feedback?

Regards Falk

Ed McGettigan schrieb:

How is that? I do not see any other way of building it. A MUX can be done in 130 transistors. For a function with 134 inputs that is pretty good. And even if you instead chose a decoder/mux combination to trade of area for speed the result is still a MUX, isn't it?

The only difference between a LUT and a MUX is, that in MUX you care about input to ouput delay, in a LUT you only care bout select to output delay.

Kolja Sulimma

Perhaps, 'start designing' means little, perhaps a better question would be when can one 'finish designing' (and ship) ! ;)

-jg

Falk,

V4 FX goes to 6.25, and we have tested for some customers just slightly higher (up to 6.5) and not seen any real yield issues. Work with your FAE.

V4 FX has so much more than V2 Pro X (which has only two devices).

Aust> Austin Lesea schrieb:

Yes, but this Austin can still be entertaining, as he waves his arms :)

eg I'm looking forward to just what exactly "equivalent static power" can be ?

Could that be like their equivalent LUTs, perhaps ?

-jg

As far as chip area goes, the decision to go to LUT6 (as we call it) was a no-brainer:

Extensive benchmarking shows that a LUT6 is 'worth" about 1.4 LUT4 (this is an average over almost 200 designs, your mileage may vary...) Our designers found that the CLB size penalty for LUT6 compared to using LUT4 in the same technology is only about 15% (Yes, the LUT takes only a small portion of the silicon area)

Gaining 40% in functional density for a 15% price in larger area is, of course, a win-win situation. The higher performance due to fewer levels of LUTs and reduced interconnects is just a bonus. Nice bonus, thank you! Peter Alfke, Xilinx

Austin Lesea wrote: ...

If using triple oxide is imitation and "Imitation is the sincerest form of flattery" then the whole semiconductor industry is using this "flattery". Did Xilinx invent the MOS transistor, self aligning gates, wire bonding, etc. and all those other things they use to produce an IC? Well, as Newton said: "If I have seen a little further it is by standing on the shoulders of Giants."

Is using a third oxid thickness really that great genuine invention nobody thought of before. Didn't the engineers at Xilinx need to bang their head fighting for this feature against many (d|m)amages seeing only the added cost? Perhaps other engineers in other companies wheren't that succesfull on the first try. Now perhaps their (d|m)amages see the light.

Otherwise congratulation to the new "baby".

And hopefully a faster release story to general availability then for XC3SE and ... and ...

Cheers

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Hi Ed,

well if you say so, but the datasheet shows

2 separate 5 input LUTs 1 output select MUX that combines the makes the 5 input LUTs to look like one 6 input LUT

if I look at that schematic from the datasheet then the 6 input function would include LUT delay and MUX in series.

if you say it is not 2 LUTs and 1 MUX, but one LUT, well then is the datasheet really confusing!!

Antti

"Kolja Sulimma" schrieb im Newsbeitrag news:4468d210$0$11063$ snipped-for-privacy@newsread4.arcor-online.net...

Hi Kolja

I am referring to my results of actual LUT delay measurements. what I did before looking the datasheet info. I was almost not to belive the lut delay (too small!) in V4. Only after seeing it in real silicon i looked up the timing info in datasheet.

Antti

Are any FX40 parts at the fab yet?

Cheers, Jon

Antti, remember how a LUT is really constructed. It contains 64 latches plus a 6-level 64-to-1 multiplexer, like a christmas tree. The data sheet just (for tutorial purposes) shows the final stage of this big multiplexer separately. If that bothers you, ignore it. But just do not believe that it costs more than the extra delay of any multiplexer level. There are 6 levels of multiplexing, nothing we can do about it. Peter Alfke

Quoth Uwe:

... yeah, but oft-forgotten is that Newton was being a dick. He wrote that in a letter to Hooke, who was notoriously short of stature, while they were arguing over who was the first for some discovery or other...

It's often quoted as if Newton was being humble, but what he was saying was "I'm better than you, and nothing you have done was remotely useful to science"...

Simon

Jim,

Basically, equivalent in this sense is "equal."

So if the static power was 1 watt before, it is still one watt (or less).

At 65nm, there is gate leakage.

Gate leakage does not vary with temperature.

So there is a component of the static power that remains the same at

-40C, or at 25C, or even at 100C.

That factor is a significant part of the static leakage. Basically, the cost of using 65nm.

What you will find is that the typical static current for Vccint (Iccint) for V5 is at first, larger than what you would expect. However, it will be on par, or below what the 100C number was for the V4. If the worst case for V4 at 100C was X watts, then a similar sized V5 will be X watts or less over the entire tempeature range, without a huge difference from 25C to 100C (which was what folks are used to seeing before gate leakage became a dominant factor in 65nm).

Does this answer the question?

Aust> John_H wrote:

Uwe,

Easy for you to say now. But there was a time where the competition was selling against triple oxide as being too new, too risky, and too expensive (with no benefit).

So, humor me, name the chips that use a triple oxide process.

Aust> Aust> ...