Howdy Gang !
It seems we have some sort of a problem with system reset in one of our SoC.
It appears that after the board power up we have to press the external rest button to get the system 100% operational. Before hitting the rest button, it seems as most of the system is working but some parts are working "strangely".
I have not traced the problem yet, as it is rather a complex SoC ...
So I have a generic question to the group:
My understanding was that all flops will be cleared automatically after the FPGA has been configured. How does the FPGA know which FLOPS have to be initialized to a '1' vs. a '0' ?
How should I implement the rest such that it would specifically be asserted after FPGA configuration is done. Do I have to connect the GSR signal to my reset signal ? There seems to be very little inconclusive guidelines for this problem.
Any pointers/information highly appreciated !
Best Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services,