I'm prototyping a design on an Altera NIOS evaluation board with an EP2C35. The design will eventually be targeted at a much smaller device, possibly an EP2C5.
I have a couple of FIR filters that I want implemented in the FPGA fabric rather than in the dedicated multipliers so I can guage the footprint/performance. Quartus keeps using the multipliers and I can't work out how to stop it.
Can anyone help?
Nial
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