Hello,
I'd appreciate some help on two questions I have relating to the SRL16E_1 primitive.
Q1. What is the correct instantiation template for the SRL16E_1 primitive in VHDL?
When I synthesise my VHDL code (see end of message) I get the following warnings:
WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:79 - Model 'SRL16E_1' has different characteristics in destination library WARNING:Xst:80 - Model name has been changed to 'SRL16E_11'
When I change the instantiated component name to SRL16E_11 I no longer get the warnings but I get errors at ngdbuild like the following:
ERROR:NgdBuild:604 - logical block 'cell6' with type 'SRL16E_11' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'SRL16E_11' is not supported in target 'virtex2'.
Q2. How do I find minimum period between the SRL16 clock and capturing the resulting Q in the flip-flop?
Eric. ps I am using ISE 6.1.03i and XST.
library ieee; use ieee.std_logic_1164.all;
entity ten_srl16s is port( Clock : in std_logic; CE : in std_logic; NewContent : in std_logic_vector (9 downto 0); Stimulus : in std_logic_vector(3 downto 0); Output : out std_logic_vector(9 downto 0) ); end ten_srl16s;
architecture structure of ten_srl16s is signal tempoutput : std_logic_vector(9 downto 0);
component SRL16E_1 port (Q : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; CE : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC ); end component;
begin -- Instantiate the 10 srl16s instantiatesrl16s: for i in 0 to 9 generate cell : SRL16E_1 port map(Q=>tempoutput(i), A0=>stimulus(0), A1=>stimulus(1), A2=>stimulus(2), A3=>stimulus(3), CE=>CE, C=>Clock, D=>newcontent(i) ); end generate;
process(Clock) variable answer : std_logic_vector(9 downto 0); begin Output