I am currently designing an RLDRAM-II controller in a Xilinx Virtex-II Pro with the following specifications:
Device = MT49H8M36FM-5 Array = 1 device deep x 4 devices wide (8 Meg x 144) Speed = 175 MHz
Mode value = 388 hex Configuration = 1 (RC = 4, RL=4, WL=5) Burst length = 4 Address bus = nonmultiplexed DLL = enabled Impedance matching = external On-die termination = enabled
The design works well except for one major problem. When reading a four data-phase burst, the third and fourth data-phase contains identical data. The value for phase three is duplicated in phase four. If the written data is A-B-C-D, the read data will be A-B-C-C.
This symptom is permanent and identical over the entire width and depth of the memory space. There is reason to believe that the problem is not caused by an incorrect write sequence, because random data in memory after power-on is read back with the same symptom (identical data in third and fourth data-phase).
The problem is probably not caused by data capture either, because I am observing the read data just after the input flip-flops (using Xilinx ChipScope). I have been delaying the read clock (QK) over one clock period in 300 ps intervals and can never see the correct data sequence.
Have you seen this problem earlier? Are the RAM devices in an invalid state? Can an incorrect initialization sequence cause this kind of behavior? I have implemented the initialization sequence according to the data sheet.
Thanks in advance.
Best regards Elling Diesen VMETRO asa Oslo, Norway