Ralph,
Sorry for the delay in my response. I tried the code below with ISE
5.2i sp3 targeting a 9572:library IEEE; use IEEE.STD_LOGIC_1164.ALL;
entity inits is Port ( d : in std_logic; c : in std_logic; q : out std_logic); end inits;
architecture inits_arch of inits is
signal q_temp : std_logic := '1';
begin
process (c) is begin if c'event and c = '1' then
q_temp "11111");
begin
process (c) is begin if c'event and c = '1' then
q_temp >Ralph,
>
>>Another method (aside from passing an INIT) is to initialize the signal
>>that will be registered:
>>
>>library ieee;
>>ues ieee.std_logic_1164.all;
>>
>>entity ff is
>>port (d, c : in std_logic;
>> q : out std_logic);
>>end entity;
>>
>>architecture ff_arch of ff is
>>signal q_temp : std_logic := '0';