Re: Xlilin xc9572XL Default register values

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Ralph,

Sorry for the delay in my response.  I tried the code below with ISE
5.2i sp3 targeting a 9572:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;

    entity inits is
        Port ( d : in std_logic;
               c : in std_logic;
               q : out std_logic);
    end inits;

    architecture inits_arch of inits is

    signal q_temp : std_logic := '1';

    begin

    process (c) is begin
    if c'event and c = '1' then

    q_temp <= d;

    end if;
    end process;

    q <= q_temp;

    end inits_arch;

The register had the INIT value of '1' attached to it.  I then tried the
below code with record types:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;

    entity inits is
        Port ( d1 : in std_logic_vector (4 downto 0);
               d2 : in std_logic_vector (4 downto 0);
               c : in std_logic;
               q1 : out std_logic_vector (4 downto 0);
               q2 : out std_logic_vector (4 downto 0));
    end inits;

    architecture inits_arch of inits is

    type v_reg_type is record
            -- registers
            IOLatch     :   std_logic_vector(4 downto 0);
            IOLatch2     :   std_logic_vector(4 downto 0);
        end record;

    signal d_temp : v_reg_type;
    signal q_temp : v_reg_type := (IOLatch => "11111", IOLatch2 => "11111");

    begin

    process (c) is begin
    if c'event and c = '1' then

    q_temp <= d_temp;

    end if;
    end process;

    d_temp.IOLatch <= d1;
    d_temp.IOLatch2 <= d2;

    q1 <= q_temp.IOLatch;
    q2 <= q_temp.IOLatch2;

    end inits_arch;

The registers did not get initialized in 5.2i sp3 or in our next version
of the software.  I will file a bug report on this.

As for your version of webpack not working please try the latest
version.  If the register is still not initializing as suspected (not
using record types that is) please contact the hotline.

thanks

Steve


Ralph Mason wrote:

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Ralph,<br>
<br>
Sorry for the delay in my response. &nbsp;I tried the code below with ISE 5.2i
sp3 targeting a 9572:<br>
<br>
<blockquote><tt>library IEEE;</tt><br>
  <tt>use IEEE.STD_LOGIC_1164.ALL;</tt><br>
  <br>
  <tt>entity inits is</tt><br>
  <tt>&nbsp;&nbsp;&nbsp; Port ( d : in std_logic;</tt><br>
  <tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; c : in
std_logic;</tt><br>
  <tt>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp; q : out
std_logic);</tt><br>
  <tt>end inits;</tt><br>
  <br>
  <tt>architecture inits_arch of inits is</tt><br>
  <br>
  <tt>signal q_temp : std_logic := '1';</tt><br>
  <br>
  <tt>begin</tt><br>
  <br>
  <tt>process (c) is begin</tt><br>
  <tt>if c'event and c = '1' then</tt><br>
  <br>
  <tt>q_temp &lt;= d;</tt><br>
  <br>
  <tt>end if;</tt><br>
  <tt>end process;</tt><br>
  <br>
  <tt>q &lt;= q_temp;</tt><br>
  <br>
  <tt>end inits_arch;</tt><br>
</blockquote>
The register had the INIT value of '1' attached to it. &nbsp;I then tried the
below code with record types:<br>
<br>
<blockquote><tt>library IEEE;</tt><br>
  <tt>use IEEE.STD_LOGIC_1164.ALL;</tt><br>
  <br>
  <tt>entity inits is</tt><br>
  <tt>&nbsp;&nbsp;&nbsp; Port ( d1 : in std_logic_vector (4 downto 0);</tt><br>
  <tt>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp; d2 : in
std_logic_vector (4 downto 0);</tt><br>
  <tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; c : in
std_logic;</tt><br>
  <tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; q1 : out
std_logic_vector (4 downto 0);</tt><br>
  <tt>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp; q2 : out
std_logic_vector (4 downto 0));</tt><br>
  <tt>end inits;</tt><br>
  <br>
  <tt>architecture inits_arch of inits is</tt><br>
  <br>
  <tt>type v_reg_type is record</tt><br>
  <tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; -- registers</tt><br>
  <tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; IOLatch&nbsp;&nbsp;&nbsp;&nbsp;
:&nbsp;&nbsp; std_logic_vector(4 downto 0);</tt><br>
  <tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
IOLatch2&nbsp;&nbsp;&nbsp;&nbsp; :&nbsp;&nbsp; std_logic_vector(4 downto
0);</tt><br>
  <tt>&nbsp;&nbsp;&nbsp; end record;</tt><br>
  <br>
  <tt>signal d_temp : v_reg_type;</tt><br>
  <tt>signal q_temp : v_reg_type := (IOLatch =&gt; "11111", IOLatch2 =&gt;
"11111");</tt><br>
  <br>
  <tt>begin</tt><br>
  <br>
  <tt>process (c) is begin</tt><br>
  <tt>if c'event and c = '1' then</tt><br>
  <br>
  <tt>q_temp &lt;= d_temp;</tt><br>
  <br>
  <tt>end if;</tt><br>
  <tt>end process;</tt><br>
  <br>
  <tt>d_temp.IOLatch &lt;= d1;</tt><br>
  <tt>d_temp.IOLatch2 &lt;= d2;</tt><br>
  <br>
  <tt>q1 &lt;= q_temp.IOLatch;</tt><br>
  <tt>q2 &lt;= q_temp.IOLatch2;</tt><br>
  <br>
  <tt>end inits_arch;</tt><br>
</blockquote>
The registers did not get initialized in 5.2i sp3 or in our next version
of the software. &nbsp;I will file a bug report on this.<br>
<br>
As for your version of webpack not working please try the latest version.
&nbsp;If the register is still not initializing as suspected (not using record
types that is) please contact the hotline.<br>
<br>
thanks<br>
<br>
Steve<br>
<br>
<br>
Ralph Mason wrote:<br>
<blockquote type="cite"
 cite="mid3VRLa.59287$ snipped-for-privacy@news.xtra.co.nz">
  <pre wrap="">"Steven Elzinga" <a class="moz-txt-link-rfc2396E"
wrote in message
<a class="moz-txt-link-freetext"
  </pre>
  <blockquote type="cite">
    <pre wrap="">Ralph,

Another method (aside from passing an INIT) is to initialize the signal
that will be registered:

library ieee;
ues ieee.std_logic_1164.all;

entity ff is
port (d, c : in std_logic;
      q : out std_logic);
end entity;

architecture ff_arch of ff is
signal q_temp : std_logic := '0';  -- XST will pass the proper INIT
value based off of the signal initialization
                                   -- This INIT value is the state to
which the register will power up
                                   -- q_temp is the signal that will be
registered
begin
:
:


Steve

    </pre>
  </blockquote>
  <pre wrap=""><!---->
Hi Steve,

With webpack 5.1 this doesn't seem to work at all. Doing this and then
looking at the report file there is no change in the init states of the
registers do not change at all.

Taking the inferred net names from the synthesis report and using a
constraints file worked fine though.

Any ideas why your approach wouldn't work for me?  Perhaps I am doing
something wrong?

Thanks
Ralph


  </pre>
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Re: Xlilin xc9572XL Default register values

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"11111");
Quoted text here. Click to load it

I don't really have allot of time to spend with this now (it's working fine
with the constraints file).

I will say however, that when the record initisation didn't work I tried
initializing another 16 bit register in the design using the same method:

 signal latchedAddress : std_logic_vector(15 downto 0)  :=
"1010101010101010";

This didn't work either. Perhaps 5.1 is to old

Thanks for the help.

Regards
Ralph



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