Hello all,
I am evaluating the use of a Xilinx XC9572XL CPLD vs. standard logic hardware for the glue logic between a Spartan II FPGA and an on-board FLASH device used to store the configuration bit stream. This mainly follows the idea presented in XAPP079 only that the configuration mode will be Slave Parallel. Specifically, I found it impossible to calculate the overall propagation delay of the (ripple?) counter presented in the design which is needed to determine the maximum clock frequency fed to the FLASH address counter. I am looking for something similar to the CLB FF delay timings in the FPGA data sheets.
Anyone know how to determine said delay without actually implementing and measuring it ?
Thanks and regards, Christian Boehme