Hi there
I'm not very familar with HDL, but I have to realize a small project with Lattice CPLD. Up to now the most things are working fine, but now I need help: I'm searching for a device to implement (possibly written in ABEL) to decode signals from PC's seriell port, so I finaly get my eight data bits, under consideration of parity bit. I think, the need for this part is very common, but I can't find it.
Can somebody help my with the code or can send a source for ABEL-code??
Greetings
Timo
What you need is a "UART receiver" and yes, they are very common. Typically you need a clock that runs at least 16x faster than the desired Baud rate. You can then detect the start bit and locate the middle of that bit position using a counter; then leave the same counter running, and use its value to determine when to sample the remaining 8 bits + optional parity bit + stop bit. Each data bit then must be shifted into a shift register, and as soon as you see a valid stop bit you must copy that shift register to a holding (buffer) register that the CPU or other "data user" can see.
The whole thing uses quite a lot of flip-flops and you may find that it will consume a big part of your CPLD. Expect to use around 30 flip-flops (9-bit shifter, 8-bit buffer, 3 bits of status information, 4-bit shift counter, 4-bit oversampling counter, possibly a few bits of state logic). If you need flexibility (variable Baud rate, configurable parity etc) then the flop count will rise yet further.
HTH
-- Jonathan Bromley, Consultant
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