There is no such thing as "normal execution time" for a testbench. It depends of course on your simulation system (P3 800 MHz has other Perfomance than a P4 3GHz). Further on the complexity of your design, next point is the average switching frequency for your design, as a simulator needs to calculate every signal switching. Another point is the testbench itself. You could programm fast testbenches or slow testbenches. A testbench using only sequential signalassignments an wait statements will be quite faster than a testbench, that calculates the stimuli and waittimes or reads them from external stimuli files.
Functional tests with Fpgas are typicaly done, when your satisfied about your simulation results. When doing a functional test, your debugging the whole system without exactly knowing wheter a failure was indicated by false logic inside the fpga.
You could use property checking, model checking and equivalence checking as further methods to ensure the functionality of your design. Static timing analyses is done to verify the timing behavior of your netlist.
bye Thomas