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RAM Synthesized away

Hi,

I use an RAM Block of 28x64 words in my design (Ouartus II 4.2 SP1). I have built the RAM with the integrated MegaFunction Editior. The problem is that this nice SRAMBlock is synthesized away ( Warning: Synthesized away node

4ksram:srama|altsyncram:altsyncram_component|altsyncram_j3u:auto_generated|ram_block1a0" ... up to 27) When I add JTAG capability or add direct output pins I can see that writing into the RAM works(Functional Simulation), because in this case the RAM is not Synthesized away. In the Quartus II Manual I read that in some conditions this may happen and they say that the help may help, but I can not find anything about this in the help. I use the RAM as a ring buffer I read Adress A put this into an register an write a new value to Adress A I got from outside, after this I add one to the Adress Counter (running i circles for the Adress counter works). I hope you can help me and tell me what I did wrong and what I can do to make it work.

Thanks in advance for your help.

With best regards.

Alex

Reply to
Alexander Korff
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Don't know this software but perhpas there is a switch to keep it from optimizing the SRAM away. Can you bring the SRAM outputs to IOs?

Reply to
Brad Smallridge

This is usually indicative of a problem with the synthesis tool thinking that the RAM (or any block synthesize away) is not used. Typically because the outputs go to another block which is also synthesized away because of a syntax error. When you add chipscope or bring pins to output .. then suddenly RAM is not synthesized away because outputs used elsewhere.

So two techniques to isolate are : [1] If the outputs go from blk A to blk B to Blk C, etc . Bring first the outputs of block A to I/O pins ... if there e error is in block A ... block A and Ram will be trimmed away. If not ... keep moving outputs down the chain until block disappears. This can slip through if there is a subtle port mismatch in width .... or a name mismatch within offending block.

[2] Easier way is to use a simulator. Tie all inputs to a known level ... and start to track forward flow of signals until Z's start to show up ... this means nets are not driven.

If you are not using a simulator ... take the effort to learn ... Quite easy once you get over the learning curve ... curve can be shortened quite a bit with sample test benches ... scripts to follow ... but payback is huge.

Regards, John Retta Owner and Designer Retta Technical Consulting Inc.

email : snipped-for-privacy@rtc-inc.com web :

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Reply to
John Retta

I did this and then the RAM is not synthesized away.

Alex

Reply to
Alexander Korff

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