Hello,
according Xilinx Homepage
formatting link
my FPGA (XC2V1000) should have 720 kbit Block-RAM. But if I look into it, using the FPGA Editor a Blockram has two units each 2048*9 bits e.g. furthermore the whole FPGA has 4x10 RAM blocks. This results in
2048*9 * 2 * 4 * 10 = 1440 kbit, of course twice of Xilinx' specification. Since 4 columns and 10 rows are surely right, the presumption of 2 units per block has to be wrong.
Please point me out where I'm wrong!
Bye Tom.