Problems with custom IP in Xilinx Project Navigator

Hi there,

I've been trying to build a verilog module wrapping a DCM and an IBUFGDS, which inputs a differential 62.5 MHz clock source for feeding into the Xilinx GEMAC core. Most of this project is being built in XPS, with the actual synthesis being done in Project Navigator.

However, I keep get warnings in Project Navigator when I build my design about nets that aren't on my DCM wrapper. I tried scaling my verilog back until I contained just a IBUFGDS, and then to just an OR gate (for testing purposes), and still I get these errors:

ERROR:NgdBuild:455 - logical net 'diff_clk_input_0/N309678' has multiple drivers. The possible drivers causing this are: pin G on block diff_clk_input_0/XST_GND with type GND, pin PAD on block diff_clk_input_0/N309678 with type PAD ERROR:NgdBuild:466 - input pad net 'diff_clk_input_0/N309678' has illegal connection. Possible pins causing this are: pin G on block diff_clk_input_0/XST_GND with type GND

My verilog module is called diff_clk_input and the instance name in XPS is diff_clk_input_0.

Nowhere in any file can I find reference to XST_GND or N309678 (the number after N changes every time I try a new design revision).

I tried playing about the with ..._xst.scr file options, but that didn't seem to help.

Anyone have any ideas? It's a really stupid little thing to be stuck on, but it's holding me up completely.

Cheers,